JP2008512682A5 - - Google Patents

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Publication number
JP2008512682A5
JP2008512682A5 JP2007531379A JP2007531379A JP2008512682A5 JP 2008512682 A5 JP2008512682 A5 JP 2008512682A5 JP 2007531379 A JP2007531379 A JP 2007531379A JP 2007531379 A JP2007531379 A JP 2007531379A JP 2008512682 A5 JP2008512682 A5 JP 2008512682A5
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JP
Japan
Prior art keywords
buffer
test
delay
bypass element
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007531379A
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English (en)
Japanese (ja)
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JP2008512682A (ja
JP4950051B2 (ja
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Publication date
Priority claimed from US10/937,470 external-priority patent/US7453258B2/en
Application filed filed Critical
Publication of JP2008512682A publication Critical patent/JP2008512682A/ja
Publication of JP2008512682A5 publication Critical patent/JP2008512682A5/ja
Application granted granted Critical
Publication of JP4950051B2 publication Critical patent/JP4950051B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007531379A 2004-09-09 2005-09-08 遠隔でテストチャンネルをバッファリングする装置 Expired - Fee Related JP4950051B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/937,470 US7453258B2 (en) 2004-09-09 2004-09-09 Method and apparatus for remotely buffering test channels
US10/937,470 2004-09-09
PCT/US2005/032202 WO2006029340A2 (en) 2004-09-09 2005-09-08 Method and apparatus for remotely buffering test channels

Publications (3)

Publication Number Publication Date
JP2008512682A JP2008512682A (ja) 2008-04-24
JP2008512682A5 true JP2008512682A5 (enExample) 2008-10-23
JP4950051B2 JP4950051B2 (ja) 2012-06-13

Family

ID=35995565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007531379A Expired - Fee Related JP4950051B2 (ja) 2004-09-09 2005-09-08 遠隔でテストチャンネルをバッファリングする装置

Country Status (7)

Country Link
US (2) US7453258B2 (enExample)
EP (1) EP1794607A2 (enExample)
JP (1) JP4950051B2 (enExample)
KR (1) KR101207090B1 (enExample)
CN (2) CN102053221A (enExample)
TW (1) TWI401447B (enExample)
WO (1) WO2006029340A2 (enExample)

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TWI467195B (zh) * 2013-06-17 2015-01-01 Ardentek Corp 測試系統之接觸界面檢測法
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US9696376B2 (en) * 2015-03-12 2017-07-04 Globalfoundries Inc. Leakage testing of integrated circuits using a logarithmic transducer and a voltmeter
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JP6782134B2 (ja) * 2016-09-26 2020-11-11 ラピスセミコンダクタ株式会社 スキャン回路、集合スキャン回路、半導体装置、および半導体装置の検査方法
KR102336181B1 (ko) 2017-06-07 2021-12-07 삼성전자주식회사 누설 전류 측정 회로, 이를 포함하는 집적 회로 및 시스템
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KR102549004B1 (ko) * 2018-06-22 2023-06-29 삼성디스플레이 주식회사 점등 검사 장치, 점등 검사 방법 및 점등 검사 시스템
KR102801426B1 (ko) * 2020-08-19 2025-04-29 삼성전자주식회사 수신 회로, 이를 포함하는 인쇄 회로 기판 및 인터페이스 회로
KR102849291B1 (ko) * 2020-09-22 2025-08-25 삼성전자주식회사 프로브 장치, 테스트 장치, 및 반도체 장치의 테스트 방법
US11313903B2 (en) * 2020-09-30 2022-04-26 Analog Devices, Inc. Pin driver and test equipment calibration
CN113866589A (zh) * 2021-09-03 2021-12-31 长江存储科技有限责任公司 芯片测试装置及芯片测试方法

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