JP2007067016A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2007067016A JP2007067016A JP2005248398A JP2005248398A JP2007067016A JP 2007067016 A JP2007067016 A JP 2007067016A JP 2005248398 A JP2005248398 A JP 2005248398A JP 2005248398 A JP2005248398 A JP 2005248398A JP 2007067016 A JP2007067016 A JP 2007067016A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode pad
- semiconductor element
- electrode
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02313—Subtractive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0239—Material of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
- H01L2224/06182—On opposite sides of the body with specially adapted redistribution layers [RDL]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
【解決手段】 半導体装置50は、貫通電極56を介してAl電極パッド20と再配線パターン52とを接続し、半導体素子14の再配線パターン52と配線基板12上の配線パターン24とをはんだバンプ58を介してフリップチップで接続する構成となっている。半導体素子14の上面には、デバイス形成層18と複数のAl電極パッド20が形成されている。Al電極パッド20と再配線パターン52との間には、半導体素子14を貫通する貫通孔54がドライエッチングにより設けられ、貫通孔54の内部には、Cuめっきにより貫通電極56が形成される。デバイス形成層18は、半導体素子14の上面に配置され、受光または発光が容易に行なえる。
【選択図】 図2
Description
図4A〜図4Eは実施例1の半導体装置の製造方法の開口形成工程(その1〜5)を説明するための図である。図4Aに示す工程において、半導体素子14を形成するための平板状のシリコン材料(シリコン基板)を用意する。そして、例えば、シリコン基板をダイシング工程により、所定寸法の半導体素子14を切り出す。半導体素子14の絶縁層(SiO2)62の上面に、デバイス形成層18が形成し、さらにデバイス形成層18の周辺にはAl電極パッド20を蒸着などの薄膜形成方法により形成する。また、絶縁層62の表面及びAl電極パッド20の上面中央部を除く表面には、SiNやポリイミド等のパッシベーション層26を積層する。Al電極パッド20は、上面がパッシベーション層26の開口80により露出される。本実施例では、開口80の直径が120μmに設定されており、この開口80の形状によって貫通電極56の鍔状接続部56aの輪郭形状が決まる。
図5A〜図5Eは実施例1の半導体装置の製造方法の絶縁層形成工程(その1〜5)を説明するための図である。図5Aに示す工程において、第1レジスト層82の上面に保護フィルム90を貼着する。この保護フィルム90は、デバイス形成層を保護すると共に、貫通孔54に連通された開口84,86を上面側から閉塞する。
図6A〜図6Dは実施例1の半導体装置の製造方法の貫通電極形成工程及び電極パッドとの導通確保工程(その1〜4)を説明するための図である。図6Aに示す工程において、Al電極パッド20及びAl電極パッド20の開口84及び開口98の内側にCr層とCu層からなるCr/Cu保護膜64をスパッタ法などの薄膜形成法を用いて形成する。
図7A〜図7Eは実施例1の半導体装置の製造方法の再配線及びレジスト除去工程(その1〜5)を説明するための図である。図7Aに示す工程において、半導体素子14の下面(裏面)の平坦化処理を行う。この平坦化処理では、Cu給電層102を除去した後、接着層100を剥離し、その後絶縁層68の下面を研磨して平坦化する。
図8A〜図8Fは実施例2の半導体装置の製造方法の開口形成工程(その1〜6)を説明するための図である。図8Aに示す工程において、半導体素子14を形成するための平板状のシリコン材料(シリコン基板)を用意する。そして、例えば、シリコン基板をダイシング工程により、所定寸法の半導体素子14を切り出す。半導体素子14の絶縁層(SiO2)62の上面に、デバイス形成層18が形成し、さらにデバイス形成層18の周辺にはAl電極パッド20を蒸着などの薄膜形成方法により形成する。また、絶縁層62の表面及びAl電極パッド20の上面中央部を除く表面には、パッシベーション層26を積層する。Al電極パッド20は、上面がパッシベーション層26の開口80により露出される。本実施例では、開口80の直径が120μmに設定されており、この開口80の形状によって貫通電極56の鍔状接続部56aの輪郭形状が決まる。
図9A〜図9Fは実施例2の半導体装置の製造方法の絶縁層形成工程(その1〜6)を説明するための図である。図9Aに示す工程において、第1レジスト層82の上面に樹脂からなる保護フィルム90を貼着する。この保護フィルム90は、デバイス形成層18を保護すると共に、貫通孔54に連通された開口84,86を上面側から閉塞する。
図10A〜図10Dは実施例2の半導体装置の製造方法の貫通電極形成工程及び電極パッドとの導通確保工程(その1〜4)を説明するための図である。図10Aに示す工程において、絶縁層68の下面に接着フィルム等による接着層100の粘着性を利用してCu給電層102を接着する。このCu給電層102は電解めっきを行なう際のめっき電極となる。
図11A〜図11Fは実施例2の半導体装置の製造方法の再配線及びレジスト除去工程(その1〜6)を説明するための図である。図11Aに示す工程において、半導体素子14の下面(裏面)の平坦化処理を行う。この平坦化処理では、Cu給電層102を除去した後、接着層100を剥離し、その後絶縁層68の下面を研磨して平坦化する。
18 デバイス形成層
20 Al電極パッド
50 半導体装置
52 再配線パターン
54 貫通孔
56 貫通電極
58 はんだバンプ
62 絶縁層
64 Cr/Cu保護膜
66,72 Ni/Au電極層
68 絶縁層
70 ソルダレジスト層
82 第1レジスト層
84,86 開口
90 保護フィルム
96 第2レジスト層
100 接着層
102 Cu給電層
200 金属層
Claims (9)
- 一面側にデバイス形成層と電極パッドを有する半導体素子の前記電極パッドと前記半導体素子の他面側に形成された配線パターンとを接続する貫通電極を有する半導体装置の製造方法であって、
前記半導体素子の一面側に第1レジスト層を形成する第1工程と、
前記第1レジスト層及び前記電極パッドの中心にエッチングにより開口を形成する第2工程と、
前記半導体素子の前記開口と連通する位置に貫通孔を形成する第3工程と、
前記半導体素子の他面側及び前記貫通孔の内周に絶縁層を形成する第4工程と、
前記第1レジスト層のうち前記電極パッドの表面を覆う部分を除去する第5工程と、
前記半導体素子の他面側に給電層を形成する第6工程と、
前記給電層の前記貫通孔に対向する部分にめっきにより導電材を析出させ、前記貫通孔内及び前記電極パッドの表面に前記貫通電極を形成する第7工程と、
前記給電層を除去する第8工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第1工程は、半導体素子の一面側及び前記電極パッドの表面に金属層を形成する工程を含み、
前記第8工程は、前記金属層を除去する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第5工程は、前記第1レジスト層の表面に第2レジスト層を形成し、アッシングにより前記電極パッドの表面に積層された前記第1レジスト層を除去する工程を含むことを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第5工程は、前記第1レジスト層を除去した前記電極パッドの表面に保護膜を形成する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第5工程は、前記第2レジスト層をリフトオフして前記電極パッドの表面に積層された保護膜を除く部分の保護膜を除去する工程を含むことを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記給電層は、接着層を介して前記半導体素子の他面側に接着されたことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記貫通電極は、前記電極パッドに全周で接続される鍔状接続部と、
一端が前記鍔状接続部と一体に結合され、他端が前記半導体素子の他面側に延在するように前記貫通孔内に形成された棒状接続部と有することを特徴とする請求項1に記載の半導体装置の製造方法。 - 一面側にデバイス形成層と電極パッドを有する半導体素子の前記電極パッドと前記半導体素子の他面側に形成された配線パターンとを接続する貫通電極を有する半導体装置の製造方法であって、
前記電極パッドの中心に開口を設け、
該開口に連通し、前記半導体素子の一面側と前記半導体素子の他面側とを貫通する貫通孔を前記半導体素子に設け、
前記貫通電極は、前記電極パッドに全周で接続される鍔状接続部と、
一端が前記鍔状接続部と一体に結合され、他端が前記半導体素子板の他面側に延在するように前記貫通孔内に形成された棒状部と有することを特徴とする半導体装置。 - 前記デバイス形成層は、光を受光または発光する光機能素子であることを特徴とする請求項8に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005248398A JP4533283B2 (ja) | 2005-08-29 | 2005-08-29 | 半導体装置の製造方法 |
US11/509,716 US7745939B2 (en) | 2005-08-29 | 2006-08-25 | Semiconductor device and method of manufacturing the same |
KR1020060081114A KR101177472B1 (ko) | 2005-08-29 | 2006-08-25 | 반도체 장치 및 그 제조 방법 |
TW095131554A TW200715437A (en) | 2005-08-29 | 2006-08-28 | Semiconductor device and method of manufacturing the same |
EP06018012.2A EP1760782B1 (en) | 2005-08-29 | 2006-08-29 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005248398A JP4533283B2 (ja) | 2005-08-29 | 2005-08-29 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007067016A true JP2007067016A (ja) | 2007-03-15 |
JP4533283B2 JP4533283B2 (ja) | 2010-09-01 |
Family
ID=37103154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005248398A Active JP4533283B2 (ja) | 2005-08-29 | 2005-08-29 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7745939B2 (ja) |
EP (1) | EP1760782B1 (ja) |
JP (1) | JP4533283B2 (ja) |
KR (1) | KR101177472B1 (ja) |
TW (1) | TW200715437A (ja) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010027965A (ja) * | 2008-07-23 | 2010-02-04 | Oki Semiconductor Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2010103467A (ja) * | 2008-10-21 | 2010-05-06 | Samsung Electro-Mechanics Co Ltd | 半導体パッケージ及びその製造方法 |
JP2010103398A (ja) * | 2008-10-27 | 2010-05-06 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板及びその製造方法 |
WO2011132971A2 (ko) * | 2010-04-22 | 2011-10-27 | 재단법인 서울테크노파크 | 장벽층을 갖는 범프를 포함하는 반도체칩 및 그 제조방법 |
KR101078734B1 (ko) * | 2009-07-07 | 2011-11-02 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조방법과, 이를 이용한 스택 패키지 |
JP2012028533A (ja) * | 2010-07-22 | 2012-02-09 | Canon Inc | 基板貫通孔内への金属充填方法及び基板 |
JP2013131720A (ja) * | 2011-12-22 | 2013-07-04 | Shinko Electric Ind Co Ltd | 半導体装置、半導体パッケージ及び半導体装置の製造方法 |
JP2013165100A (ja) * | 2012-02-09 | 2013-08-22 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、回路装置、電子機器 |
JP2015144254A (ja) * | 2013-12-24 | 2015-08-06 | パナソニックIpマネジメント株式会社 | 発光デバイス、表示装置及び発光デバイスの製造方法 |
KR20160138081A (ko) | 2014-03-31 | 2016-12-02 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 반도체장치, 적층형 반도체장치, 봉지후 적층형 반도체장치, 및 이들의 제조방법 |
KR20160138082A (ko) | 2014-03-31 | 2016-12-02 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 반도체장치, 적층형 반도체장치, 봉지후 적층형 반도체장치, 및 이들의 제조방법 |
EP3103835A1 (en) | 2015-06-08 | 2016-12-14 | Shin-Etsu Chemical Co., Ltd. | Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100927749B1 (ko) * | 2008-02-13 | 2009-11-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
DE102008052244A1 (de) * | 2008-10-18 | 2010-04-22 | Carl Freudenberg Kg | Flexible Leiterplatte |
US8137995B2 (en) * | 2008-12-11 | 2012-03-20 | Stats Chippac, Ltd. | Double-sided semiconductor device and method of forming top-side and bottom-side interconnect structures |
JP2010211179A (ja) * | 2009-02-13 | 2010-09-24 | Hitachi Ltd | 光電気複合配線モジュールおよびその製造方法 |
JP5608430B2 (ja) * | 2010-06-07 | 2014-10-15 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
US20120049358A1 (en) * | 2010-08-24 | 2012-03-01 | Bin-Hong Cheng | Semiconductor Device and Semiconductor Process for Making the Same |
JP5325197B2 (ja) * | 2010-11-30 | 2013-10-23 | 豊田合成株式会社 | 発光装置およびその製造方法 |
US8927869B2 (en) * | 2012-04-11 | 2015-01-06 | International Business Machines Corporation | Semiconductor structures and methods of manufacture |
KR102021884B1 (ko) | 2012-09-25 | 2019-09-18 | 삼성전자주식회사 | 후면 본딩 구조체를 갖는 반도체 소자 |
US9865524B2 (en) * | 2013-04-08 | 2018-01-09 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation |
KR102491069B1 (ko) | 2015-12-03 | 2023-01-26 | 삼성전자주식회사 | 반도체 소자 |
US10879187B2 (en) | 2017-06-14 | 2020-12-29 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
US11348876B2 (en) | 2017-06-14 | 2022-05-31 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
KR102064079B1 (ko) | 2018-06-04 | 2020-01-08 | 삼성전기주식회사 | 인덕터 |
JP7045978B2 (ja) * | 2018-12-07 | 2022-04-01 | 三菱電機株式会社 | 半導体装置および電力変換装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094082A (ja) * | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | 光素子及びその製造方法並びに電子機器 |
JP2002373957A (ja) * | 2001-06-14 | 2002-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004221357A (ja) * | 2003-01-15 | 2004-08-05 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004235528A (ja) * | 2003-01-31 | 2004-08-19 | Mitsubishi Electric Corp | 基板の製造方法 |
JP2004327910A (ja) * | 2003-04-28 | 2004-11-18 | Sharp Corp | 半導体装置およびその製造方法 |
JP2005123325A (ja) * | 2003-10-15 | 2005-05-12 | Seiko Epson Corp | 半導体装置、回路基板、及び電子機器 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63156348A (ja) | 1986-12-19 | 1988-06-29 | Fujitsu Ltd | 半導体装置 |
JP2569789B2 (ja) | 1989-03-13 | 1997-01-08 | 富士電機株式会社 | 半導体チップの電極形成方法 |
JP3507251B2 (ja) * | 1995-09-01 | 2004-03-15 | キヤノン株式会社 | 光センサicパッケージおよびその組立方法 |
JP2000081524A (ja) * | 1998-09-07 | 2000-03-21 | Sony Corp | 光送受信システム |
JP4923336B2 (ja) * | 2001-04-10 | 2012-04-25 | 日本電気株式会社 | 回路基板及び該回路基板を用いた電子機器 |
TW546819B (en) * | 2001-05-30 | 2003-08-11 | Sharp Kk | Semiconductor device, manufacturing method thereof, and monolithic microwave integrated circuit |
US20030119308A1 (en) * | 2001-12-20 | 2003-06-26 | Geefay Frank S. | Sloped via contacts |
JP2005520333A (ja) * | 2002-03-14 | 2005-07-07 | ゼネラル ダイナミクス アドバンスド インフォメーション システムズ、インク | 多層用基板の積層技術 |
US6852627B2 (en) * | 2003-03-05 | 2005-02-08 | Micron Technology, Inc. | Conductive through wafer vias |
TWI239629B (en) * | 2003-03-17 | 2005-09-11 | Seiko Epson Corp | Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus |
JP2004311948A (ja) * | 2003-03-27 | 2004-11-04 | Seiko Epson Corp | 半導体装置、半導体デバイス、電子機器、および半導体装置の製造方法 |
JP3800335B2 (ja) * | 2003-04-16 | 2006-07-26 | セイコーエプソン株式会社 | 光デバイス、光モジュール、半導体装置及び電子機器 |
JP2004342990A (ja) * | 2003-05-19 | 2004-12-02 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
KR100541087B1 (ko) * | 2003-10-01 | 2006-01-10 | 삼성전기주식회사 | 마이크로 디바이스를 위한 웨이퍼 레벨 패키지 및 제조방법 |
US8084866B2 (en) * | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US7199439B2 (en) * | 2004-06-14 | 2007-04-03 | Micron Technology, Inc. | Microelectronic imagers and methods of packaging microelectronic imagers |
US7294897B2 (en) * | 2004-06-29 | 2007-11-13 | Micron Technology, Inc. | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
JP4349278B2 (ja) * | 2004-12-24 | 2009-10-21 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7371676B2 (en) * | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
JP4698296B2 (ja) * | 2005-06-17 | 2011-06-08 | 新光電気工業株式会社 | 貫通電極を有する半導体装置の製造方法 |
JP4983049B2 (ja) * | 2005-06-24 | 2012-07-25 | セイコーエプソン株式会社 | 半導体装置および電子機器 |
JP2007036571A (ja) * | 2005-07-26 | 2007-02-08 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
2005
- 2005-08-29 JP JP2005248398A patent/JP4533283B2/ja active Active
-
2006
- 2006-08-25 KR KR1020060081114A patent/KR101177472B1/ko active IP Right Grant
- 2006-08-25 US US11/509,716 patent/US7745939B2/en active Active
- 2006-08-28 TW TW095131554A patent/TW200715437A/zh unknown
- 2006-08-29 EP EP06018012.2A patent/EP1760782B1/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094082A (ja) * | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | 光素子及びその製造方法並びに電子機器 |
JP2002373957A (ja) * | 2001-06-14 | 2002-12-26 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004221357A (ja) * | 2003-01-15 | 2004-08-05 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004235528A (ja) * | 2003-01-31 | 2004-08-19 | Mitsubishi Electric Corp | 基板の製造方法 |
JP2004327910A (ja) * | 2003-04-28 | 2004-11-18 | Sharp Corp | 半導体装置およびその製造方法 |
JP2005123325A (ja) * | 2003-10-15 | 2005-05-12 | Seiko Epson Corp | 半導体装置、回路基板、及び電子機器 |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010027965A (ja) * | 2008-07-23 | 2010-02-04 | Oki Semiconductor Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2010103467A (ja) * | 2008-10-21 | 2010-05-06 | Samsung Electro-Mechanics Co Ltd | 半導体パッケージ及びその製造方法 |
JP2010103398A (ja) * | 2008-10-27 | 2010-05-06 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板及びその製造方法 |
KR101078734B1 (ko) * | 2009-07-07 | 2011-11-02 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조방법과, 이를 이용한 스택 패키지 |
WO2011132971A2 (ko) * | 2010-04-22 | 2011-10-27 | 재단법인 서울테크노파크 | 장벽층을 갖는 범프를 포함하는 반도체칩 및 그 제조방법 |
KR101095373B1 (ko) * | 2010-04-22 | 2011-12-16 | 재단법인 서울테크노파크 | 장벽층을 갖는 범프를 포함하는 반도체칩 및 그 제조방법 |
WO2011132971A3 (ko) * | 2010-04-22 | 2012-03-08 | 재단법인 서울테크노파크 | 장벽층을 갖는 범프를 포함하는 반도체칩 및 그 제조방법 |
JP2012028533A (ja) * | 2010-07-22 | 2012-02-09 | Canon Inc | 基板貫通孔内への金属充填方法及び基板 |
JP2013131720A (ja) * | 2011-12-22 | 2013-07-04 | Shinko Electric Ind Co Ltd | 半導体装置、半導体パッケージ及び半導体装置の製造方法 |
JP2013165100A (ja) * | 2012-02-09 | 2013-08-22 | Seiko Epson Corp | 半導体装置、半導体装置の製造方法、回路装置、電子機器 |
JP2015144254A (ja) * | 2013-12-24 | 2015-08-06 | パナソニックIpマネジメント株式会社 | 発光デバイス、表示装置及び発光デバイスの製造方法 |
KR20160138081A (ko) | 2014-03-31 | 2016-12-02 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 반도체장치, 적층형 반도체장치, 봉지후 적층형 반도체장치, 및 이들의 제조방법 |
KR20160138082A (ko) | 2014-03-31 | 2016-12-02 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 반도체장치, 적층형 반도체장치, 봉지후 적층형 반도체장치, 및 이들의 제조방법 |
US10141272B2 (en) | 2014-03-31 | 2018-11-27 | Shin-Etsu Chemical Co., Ltd. | Semiconductor apparatus, stacked semiconductor apparatus and encapsulated stacked-semiconductor apparatus each having photo-curable resin layer |
US10319653B2 (en) | 2014-03-31 | 2019-06-11 | Shin-Etsu Chemical Co., Ltd. | Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same |
EP3103835A1 (en) | 2015-06-08 | 2016-12-14 | Shin-Etsu Chemical Co., Ltd. | Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same |
KR20160144316A (ko) | 2015-06-08 | 2016-12-16 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 반도체 장치, 적층형 반도체 장치, 밀봉 후 적층형 반도체 장치 및 이들의 제조 방법 |
US9620429B2 (en) | 2015-06-08 | 2017-04-11 | Shin-Etsu Chemical Co., Ltd. | Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
KR20070026048A (ko) | 2007-03-08 |
EP1760782A3 (en) | 2012-10-31 |
JP4533283B2 (ja) | 2010-09-01 |
EP1760782B1 (en) | 2016-11-02 |
TW200715437A (en) | 2007-04-16 |
KR101177472B1 (ko) | 2012-08-28 |
US20070045746A1 (en) | 2007-03-01 |
EP1760782A2 (en) | 2007-03-07 |
US7745939B2 (en) | 2010-06-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4533283B2 (ja) | 半導体装置の製造方法 | |
JP4758712B2 (ja) | 半導体装置の製造方法 | |
JP5321873B2 (ja) | 接合パッドを具えた相互接続構造、および、接合パッド上にバンプ部位を作成する方法 | |
KR100725565B1 (ko) | 반도체 장치의 제조 방법 | |
KR100682434B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP4373866B2 (ja) | 半導体装置の製造方法 | |
JP2010045371A (ja) | 導電性保護膜を有する貫通電極構造体及びその形成方法 | |
US7528481B2 (en) | Wafer level packaging cap and fabrication method thereof | |
JP4828182B2 (ja) | 半導体装置の製造方法 | |
JP2006100435A (ja) | 半導体装置およびその製造方法 | |
JP2007036060A (ja) | 半導体装置及びその製造方法 | |
JP2010129684A (ja) | 半導体装置の製造方法および半導体装置 | |
JP2006228947A (ja) | 半導体装置の製造方法、半導体装置 | |
JP2005101268A (ja) | 半導体装置の製造方法 | |
JP2008311592A (ja) | 電子装置の製造方法 | |
JP2007266531A (ja) | 半導体装置の製造方法 | |
JP4063277B2 (ja) | 半導体装置の製造方法 | |
JP2010251791A (ja) | 半導体装置及びその製造方法 | |
JP4544902B2 (ja) | 半導体装置及びその製造方法 | |
JP2008141019A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP5313294B2 (ja) | 半導体装置 | |
JP4119740B2 (ja) | 半導体装置の製造方法 | |
JP2006120803A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2006030230A (ja) | 半導体装置の製造方法 | |
JP2009135529A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080331 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100112 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100210 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100413 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100518 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100608 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100611 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4533283 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130618 Year of fee payment: 3 |