JP2006191029A5 - - Google Patents

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Publication number
JP2006191029A5
JP2006191029A5 JP2005363874A JP2005363874A JP2006191029A5 JP 2006191029 A5 JP2006191029 A5 JP 2006191029A5 JP 2005363874 A JP2005363874 A JP 2005363874A JP 2005363874 A JP2005363874 A JP 2005363874A JP 2006191029 A5 JP2006191029 A5 JP 2006191029A5
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JP
Japan
Prior art keywords
oxide
single crystal
silicon
annealing
annealing step
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JP2005363874A
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English (en)
Japanese (ja)
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JP2006191029A (ja
JP5043333B2 (ja
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Publication date
Priority claimed from US11/031,165 external-priority patent/US8138061B2/en
Application filed filed Critical
Publication of JP2006191029A publication Critical patent/JP2006191029A/ja
Publication of JP2006191029A5 publication Critical patent/JP2006191029A5/ja
Application granted granted Critical
Publication of JP5043333B2 publication Critical patent/JP5043333B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2005363874A 2005-01-07 2005-12-16 親水性Ｓｉ表面と界面接合酸化物の溶解とを用いるＳｉ間擬似疎水性ウェハ接合 Expired - Fee Related JP5043333B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/031,165 2005-01-07
US11/031,165 US8138061B2 (en) 2005-01-07 2005-01-07 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

Publications (3)

Publication Number Publication Date
JP2006191029A JP2006191029A (ja) 2006-07-20
JP2006191029A5 true JP2006191029A5 (enExample) 2008-11-13
JP5043333B2 JP5043333B2 (ja) 2012-10-10

Family

ID=36653805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005363874A Expired - Fee Related JP5043333B2 (ja) 2005-01-07 2005-12-16 親水性Ｓｉ表面と界面接合酸化物の溶解とを用いるＳｉ間擬似疎水性ウェハ接合

Country Status (4)

Country Link
US (3) US8138061B2 (enExample)
JP (1) JP5043333B2 (enExample)
CN (1) CN1818154A (enExample)
TW (1) TW200632992A (enExample)

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JP5054509B2 (ja) * 2004-02-25 2012-10-24 ソワテク 光検出装置
US7285473B2 (en) * 2005-01-07 2007-10-23 International Business Machines Corporation Method for fabricating low-defect-density changed orientation Si
US8138061B2 (en) 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
JP2008060355A (ja) * 2006-08-31 2008-03-13 Sumco Corp 貼り合わせウェーハの製造方法および貼り合わせウェーハ
FR2910177B1 (fr) * 2006-12-18 2009-04-03 Soitec Silicon On Insulator Couche tres fine enterree
CN101548369B (zh) * 2006-12-26 2012-07-18 硅绝缘体技术有限公司 制造绝缘体上半导体结构的方法
SG144092A1 (en) * 2006-12-26 2008-07-29 Sumco Corp Method of manufacturing bonded wafer
DE602006017906D1 (de) * 2006-12-26 2010-12-09 Soitec Silicon On Insulator Verfahren zum herstellen einer halbleiter-auf-isolator-struktur
JP5009124B2 (ja) * 2007-01-04 2012-08-22 コバレントマテリアル株式会社 半導体基板の製造方法
JP5038723B2 (ja) * 2007-01-04 2012-10-03 コバレントマテリアル株式会社 半導体基板およびその製造方法
FR2911430B1 (fr) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"
WO2008096194A1 (en) 2007-02-08 2008-08-14 S.O.I.Tec Silicon On Insulator Technologies Method of fabrication of highly heat dissipative substrates
JP5256625B2 (ja) * 2007-03-05 2013-08-07 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの評価方法
JP5433927B2 (ja) * 2007-03-14 2014-03-05 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
KR101431780B1 (ko) 2007-03-19 2014-09-19 소이텍 패턴화된 얇은 ｓｏｉ
FR2918792B1 (fr) * 2007-07-10 2010-04-23 Soitec Silicon On Insulator Procede de traitement de defauts d'interface dans un substrat.
JP2011504655A (ja) * 2007-11-23 2011-02-10 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 精密な酸化物の溶解
EP2065921A1 (en) * 2007-11-29 2009-06-03 S.O.I.T.E.C. Silicon on Insulator Technologies Method for fabricating a semiconductor substrate with areas with different crystal orienation
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8148242B2 (en) * 2008-02-20 2012-04-03 Soitec Oxidation after oxide dissolution
WO2009128776A1 (en) * 2008-04-15 2009-10-22 Vallin Oerjan Hybrid wafers with hybrid-oriented layer
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
US20100178750A1 (en) * 2008-07-17 2010-07-15 Sumco Corporation Method for producing bonded wafer
JP2010072209A (ja) * 2008-09-17 2010-04-02 Fuji Xerox Co Ltd 静電荷像現像用トナー、静電荷像現像用トナーの製造方法、静電荷像現像用現像剤および画像形成装置
FR2936356B1 (fr) * 2008-09-23 2010-10-22 Soitec Silicon On Insulator Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique
JP5493345B2 (ja) * 2008-12-11 2014-05-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2964495A1 (fr) * 2010-09-02 2012-03-09 Soitec Silicon On Insulator Procede de fabrication d'une structure seoi multiple comportant une couche isolante ultrafine
FR2968450A1 (fr) * 2010-12-07 2012-06-08 Soitec Silicon On Insulator Procede de traitement d'une structure de type semi-conducteur sur isolant
KR101705937B1 (ko) * 2011-01-25 2017-02-10 에베 그룹 에. 탈너 게엠베하 웨이퍼들의 영구적 결합을 위한 방법
FR2972564B1 (fr) 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
US9378955B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US20130049178A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US20130049175A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378956B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9312133B2 (en) 2011-08-25 2016-04-12 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9396947B2 (en) 2011-08-25 2016-07-19 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
WO2013066977A1 (en) * 2011-10-31 2013-05-10 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization
CN102586886A (zh) * 2012-03-10 2012-07-18 天津市环欧半导体材料技术有限公司 一种用于去除硅晶片表面氧沉积物的硅晶片退火方法
WO2014052476A2 (en) 2012-09-25 2014-04-03 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On... Methods for wafer bonding, and for nucleating bonding nanophases
FR3007891B1 (fr) * 2013-06-28 2016-11-25 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
JP6061251B2 (ja) * 2013-07-05 2017-01-18 株式会社豊田自動織機 半導体基板の製造方法
US9601368B2 (en) * 2015-07-16 2017-03-21 Infineon Technologies Ag Semiconductor device comprising an oxygen diffusion barrier and manufacturing method
US9741685B2 (en) * 2015-08-07 2017-08-22 Lam Research Corporation Methods for directly bonding silicon to silicon or silicon carbide to silicon carbide
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
JP2020508564A (ja) * 2017-02-21 2020-03-19 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板を接合する方法および装置

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JP3175323B2 (ja) * 1991-08-26 2001-06-11 株式会社デンソー 半導体基板の製造方法
JP2820120B2 (ja) * 1996-06-03 1998-11-05 日本電気株式会社 半導体基板の製造方法
JP4273540B2 (ja) * 1998-07-21 2009-06-03 株式会社Ｓｕｍｃｏ 貼り合わせ半導体基板及びその製造方法
JP2004031715A (ja) * 2002-06-27 2004-01-29 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US7153757B2 (en) 2002-08-29 2006-12-26 Analog Devices, Inc. Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7023055B2 (en) 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US8138061B2 (en) 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US7285473B2 (en) 2005-01-07 2007-10-23 International Business Machines Corporation Method for fabricating low-defect-density changed orientation Si

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