JP5043333B2 - 親水性Ｓｉ表面と界面接合酸化物の溶解とを用いるＳｉ間擬似疎水性ウェハ接合 - Google Patents

親水性Ｓｉ表面と界面接合酸化物の溶解とを用いるＳｉ間擬似疎水性ウェハ接合 Download PDF

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JP5043333B2
JP5043333B2 JP2005363874A JP2005363874A JP5043333B2 JP 5043333 B2 JP5043333 B2 JP 5043333B2 JP 2005363874 A JP2005363874 A JP 2005363874A JP 2005363874 A JP2005363874 A JP 2005363874A JP 5043333 B2 JP5043333 B2 JP 5043333B2
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oxide
annealing
layer
bonding
wafer
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JP2006191029A (ja
JP2006191029A5 (enExample
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ジョエル・ピー・デソウザ
ジョン・エイ・オット
アレクサンダー・レズニチェック
デベンドラ・ケイ・サダナ
キャサリン・エル・シーンガー
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2005363874A 2005-01-07 2005-12-16 親水性Ｓｉ表面と界面接合酸化物の溶解とを用いるＳｉ間擬似疎水性ウェハ接合 Expired - Fee Related JP5043333B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/031,165 US8138061B2 (en) 2005-01-07 2005-01-07 Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US11/031,165 2005-01-07

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JP2006191029A JP2006191029A (ja) 2006-07-20
JP2006191029A5 JP2006191029A5 (enExample) 2008-11-13
JP5043333B2 true JP5043333B2 (ja) 2012-10-10

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JP2005363874A Expired - Fee Related JP5043333B2 (ja) 2005-01-07 2005-12-16 親水性Ｓｉ表面と界面接合酸化物の溶解とを用いるＳｉ間擬似疎水性ウェハ接合

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US (3) US8138061B2 (enExample)
JP (1) JP5043333B2 (enExample)
CN (1) CN1818154A (enExample)
TW (1) TW200632992A (enExample)

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US7285473B2 (en) * 2005-01-07 2007-10-23 International Business Machines Corporation Method for fabricating low-defect-density changed orientation Si
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
JP2008060355A (ja) * 2006-08-31 2008-03-13 Sumco Corp 貼り合わせウェーハの製造方法および貼り合わせウェーハ
FR2910177B1 (fr) * 2006-12-18 2009-04-03 Soitec Silicon On Insulator Couche tres fine enterree
SG144092A1 (en) * 2006-12-26 2008-07-29 Sumco Corp Method of manufacturing bonded wafer
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DE602006017906D1 (de) * 2006-12-26 2010-12-09 Soitec Silicon On Insulator Verfahren zum herstellen einer halbleiter-auf-isolator-struktur
JP5038723B2 (ja) * 2007-01-04 2012-10-03 コバレントマテリアル株式会社 半導体基板およびその製造方法
JP5009124B2 (ja) * 2007-01-04 2012-08-22 コバレントマテリアル株式会社 半導体基板の製造方法
FR2911430B1 (fr) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"
WO2008096194A1 (en) 2007-02-08 2008-08-14 S.O.I.Tec Silicon On Insulator Technologies Method of fabrication of highly heat dissipative substrates
JP5256625B2 (ja) * 2007-03-05 2013-08-07 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの評価方法
JP5433927B2 (ja) * 2007-03-14 2014-03-05 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
CN101636832B (zh) 2007-03-19 2012-01-11 S.O.I.Tec绝缘体上硅技术公司 形成图案的薄soi
FR2918792B1 (fr) * 2007-07-10 2010-04-23 Soitec Silicon On Insulator Procede de traitement de defauts d'interface dans un substrat.
WO2009066135A1 (en) * 2007-11-23 2009-05-28 S.O.I.Tec Silicon On Insulator Technologies Precise oxide dissolution
EP2065921A1 (en) * 2007-11-29 2009-06-03 S.O.I.T.E.C. Silicon on Insulator Technologies Method for fabricating a semiconductor substrate with areas with different crystal orienation
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5412445B2 (ja) * 2008-02-20 2014-02-12 ソイテック 酸化物溶解後の酸化
WO2009128776A1 (en) * 2008-04-15 2009-10-22 Vallin Oerjan Hybrid wafers with hybrid-oriented layer
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
US20100178750A1 (en) * 2008-07-17 2010-07-15 Sumco Corporation Method for producing bonded wafer
JP2010072209A (ja) * 2008-09-17 2010-04-02 Fuji Xerox Co Ltd 静電荷像現像用トナー、静電荷像現像用トナーの製造方法、静電荷像現像用現像剤および画像形成装置
FR2936356B1 (fr) * 2008-09-23 2010-10-22 Soitec Silicon On Insulator Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique
JP5493345B2 (ja) 2008-12-11 2014-05-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
FR2941324B1 (fr) * 2009-01-22 2011-04-29 Soitec Silicon On Insulator Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant.
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2964495A1 (fr) * 2010-09-02 2012-03-09 Soitec Silicon On Insulator Procede de fabrication d'une structure seoi multiple comportant une couche isolante ultrafine
FR2968450A1 (fr) * 2010-12-07 2012-06-08 Soitec Silicon On Insulator Procede de traitement d'une structure de type semi-conducteur sur isolant
EP3442006A3 (de) * 2011-01-25 2019-02-20 EV Group E. Thallner GmbH Verfahren zum permanenten bonden von wafern
FR2972564B1 (fr) 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
US20130049175A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378955B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US20130049178A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9396947B2 (en) 2011-08-25 2016-07-19 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9312133B2 (en) 2011-08-25 2016-04-12 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378956B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
WO2013066977A1 (en) * 2011-10-31 2013-05-10 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization
CN102586886A (zh) * 2012-03-10 2012-07-18 天津市环欧半导体材料技术有限公司 一种用于去除硅晶片表面氧沉积物的硅晶片退火方法
US9418963B2 (en) 2012-09-25 2016-08-16 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University Methods for wafer bonding, and for nucleating bonding nanophases
FR3007891B1 (fr) * 2013-06-28 2016-11-25 Soitec Silicon On Insulator Procede de fabrication d'une structure composite
JP6061251B2 (ja) * 2013-07-05 2017-01-18 株式会社豊田自動織機 半導体基板の製造方法
US9601368B2 (en) * 2015-07-16 2017-03-21 Infineon Technologies Ag Semiconductor device comprising an oxygen diffusion barrier and manufacturing method
US9741685B2 (en) * 2015-08-07 2017-08-22 Lam Research Corporation Methods for directly bonding silicon to silicon or silicon carbide to silicon carbide
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
JP2020508564A (ja) * 2017-02-21 2020-03-19 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板を接合する方法および装置

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JP2820120B2 (ja) * 1996-06-03 1998-11-05 日本電気株式会社 半導体基板の製造方法
JP4273540B2 (ja) * 1998-07-21 2009-06-03 株式会社Ｓｕｍｃｏ 貼り合わせ半導体基板及びその製造方法
JP2004031715A (ja) * 2002-06-27 2004-01-29 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
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US7023055B2 (en) 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US20050116290A1 (en) 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US8138061B2 (en) 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
US7285473B2 (en) 2005-01-07 2007-10-23 International Business Machines Corporation Method for fabricating low-defect-density changed orientation Si

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Publication number Publication date
US20120156861A1 (en) 2012-06-21
JP2006191029A (ja) 2006-07-20
US20090298258A1 (en) 2009-12-03
TW200632992A (en) 2006-09-16
CN1818154A (zh) 2006-08-16
US8138061B2 (en) 2012-03-20
US20060154442A1 (en) 2006-07-13
US8053330B2 (en) 2011-11-08

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