JP5412445B2 - 酸化物溶解後の酸化 - Google Patents
酸化物溶解後の酸化 Download PDFInfo
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- JP5412445B2 JP5412445B2 JP2010547263A JP2010547263A JP5412445B2 JP 5412445 B2 JP5412445 B2 JP 5412445B2 JP 2010547263 A JP2010547263 A JP 2010547263A JP 2010547263 A JP2010547263 A JP 2010547263A JP 5412445 B2 JP5412445 B2 JP 5412445B2
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- 238000004090 dissolution Methods 0.000 title claims description 36
- 230000003647 oxidation Effects 0.000 title claims description 32
- 238000007254 oxidation reaction Methods 0.000 title claims description 32
- 238000000034 method Methods 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 50
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000001590 oxidative effect Effects 0.000 claims description 10
- 238000005137 deposition process Methods 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000006392 deoxygenation reaction Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 239000002243 precursor Substances 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000005019 vapor deposition process Methods 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013068 control sample Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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Description
前記基板は、
−1以上の半導体材料からなる作用薄層、
−支持層、及び
−前記作用層と支持層の間の酸化物薄層とからなり、
前記方法は、
−前記埋没酸化物薄層が必要とする厚さ以上の厚さを有する埋没酸化物薄層(Thin BuriedOxide Layer)を備えたSeOIの中間層を製造する工程、及び
−前記埋没酸化物層を溶解して、そこに前記埋没酸化物薄層を形成する前記埋没酸化物層の溶解工程とからなる。
−シリコンのような1以上の半導体から製造される作用薄層、
−支持層、及び
−前記作用層と前記支持層の間の埋没酸化物(BOX)層を含む基板として理解される。
−低Dit値とは1×1012 cm‐2eV‐1未満の数値を意味し、
−高電荷移動度とは、500 cm 2 V -1 s ‐1 以上の電荷移動度を意味すると明記される。
−1つ以上の半導体からなる作用層、
−支持層、及び
−前記作用層と前記支持層の間の埋没酸化物薄層を含み、
前記方法は、
−前記埋没酸化物薄層が必要とするよりも厚みのある埋没酸化物薄層を有するSeOI基板中間体を製造する工程、
−前記埋没酸化物層を溶解し、それによって前記埋没酸化物薄層を形成する工程、
前記溶解工程後、前記基板上に酸化物層を形成するための前記基板の酸化工程、及び
前記基板の前記電気的界面品質を向上し、Dit値を減少さるために、すくなくとも前記酸化物層の一部が、前記作用層を通して拡散するための酸化物の移動工程を含むことを特徴とする方法である。
−前記酸化工程中の前記酸化温度は1100℃から1150℃からなり、
−前記酸化工程は30分未満であり、
−前記酸化工程は2分未満であり、
−前記酸化工程が酸化物堆積処理で、温度は900℃未満で行われ、
−酸化物堆積処理後、熱処理が1100℃から1150℃の間を含む温度で行われ、
−酸化物堆積処理は化学蒸着、低圧化学蒸着処理、原子層蒸着処理、またはプラズマ化学気相蒸着処理であり、
−前記酸化物蒸着処理はテトラエチルオルトケイ酸塩(tetraethylorthosilicate)を前駆物質として用いる低圧化学蒸着処理であり、
−脱酸素工程が酸化処理後に行われ、
−酸化処理前の作用層は55 nmより薄く、
−溶解処理は主に前記埋没酸化物層の局所的な島状構造物部分(local island(s))上で行われる。
四角は、溶解処理に施され異なる厚みのSi作用層11を備えるSeOI試料のDit測定値を表わす記号である。
及び、菱形は前記Si作用層11と同じ厚みを有するSeOI対照試料のDit測定値を表わす記号であるが、溶解処理を実行していない。
前記二酸化ケイ素は前記作用層11上に堆積する。
本発明の前記第一と第三の実施形態において、前記酸化処理は脱酸素工程の後、約10分後に続く。このような脱酸素工程は例としてHF処理を通して行われる。前記脱酸素工程は、前記UTBOX基板1上の、硬化工程の後の前記残存酸素層の除去のために行われる。
Claims (11)
- 薄酸化物を有するSeOI基板(1)を製造する方法であって、
前記基板は、
a)1以上の半導体材料より製造された作用薄層(11)、
b)支持層、及び
c)作用層と支持層の間の埋没酸化物薄層(12)からなり、
前記方法は、
d)前記埋没酸化物薄層に求められる厚み以上の厚みの埋没薄酸化物(12)を備える中間SeOI基板を製造する工程、
e)前記埋没薄酸化物(12)を溶解し、それによって前記埋没酸化物薄層を形成する工程と、を含み、
前記方法は、
前記溶解工程後、酸化物層(13)を基質上に製造するための酸化工程と、
電気的界面品質を向上させ、Dit値を減少するために、少なくとも酸化物層の一部が作用層を通して拡散するための、1100℃〜1150℃の温度で処理する酸化物移動工程と、
を含むことを特徴とする方法。 - 酸化物の溶解処理を実行して、埋没酸化物薄層を有するSeOI基板の界面品質を改良する方法であって、
前記方法は、
基板上に酸化物層を製造するために前記基板の酸化工程、及び
前記基板の電気的界面品質を向上させ、そのDit値を減少させるために、少なくとも酸化物層の一部が、作用層を通して拡散するための、1100℃〜1150℃の温度で処理する酸化物移動工程と、
を含むことを特徴とする方法。 - 請求項1又は2に記載の方法であって、さらに前記酸化工程の間、酸化温度が1100℃から1150℃であることを特徴とする方法。
- 請求項1〜3のいずれか一項に記載の方法であって、さらに前記酸化工程が30分未満で実行されることを特徴とする方法。
- 請求項1〜3のいずれか一項に記載の方法であって、さらに前記酸化工程が2分未満で実行されることを特徴とする方法。
- 請求項1又は2に記載の方法であって、前記酸化工程が、酸化物の堆積処理工程であって、900℃未満の温度で実行されることを特徴とする方法。
- 請求項6に記載の方法であって、酸化堆積処理が化学蒸着堆積処理、低圧化学蒸着堆積処理、原子層蒸着処理、またはプラズマ化学気相蒸着処理であることを特徴とする方法。
- 請求項1〜7のいずれか一項に記載の方法であって、前記酸化蒸着処理が低圧化学蒸着堆積処理であって、前駆物質としてテトラエチルオルトケイ酸塩が使われることを特徴とする方法。
- 請求項4、6〜8のいずれか一項に記載の方法であって、前記酸化処理後に脱酸素処理が実行されることを特徴とする方法。
- 請求項1〜9のいずれか一項に記載の方法であって、前記作用層が前記酸化処理前に55nmよりも薄いことを特徴とする方法。
- 請求項1〜10のいずれか一項に記載の方法であって、前記溶解工程が主に前記埋没酸化物層の局所的な島状構造部分で実行されることを特徴とする方法。
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PCT/IB2008/051801 WO2009104060A1 (en) | 2008-02-20 | 2008-02-20 | Oxidation after oxide dissolution |
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JP2011512685A JP2011512685A (ja) | 2011-04-21 |
JP5412445B2 true JP5412445B2 (ja) | 2014-02-12 |
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US (1) | US8148242B2 (ja) |
JP (1) | JP5412445B2 (ja) |
DE (1) | DE112008003726B4 (ja) |
TW (1) | TWI378538B (ja) |
WO (1) | WO2009104060A1 (ja) |
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US8508289B2 (en) | 2009-12-08 | 2013-08-13 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
FR2953643B1 (fr) | 2009-12-08 | 2012-07-27 | Soitec Silicon On Insulator | Cellule memoire flash sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
FR2953641B1 (fr) | 2009-12-08 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Circuit de transistors homogenes sur seoi avec grille de controle arriere enterree sous la couche isolante |
FR2957193B1 (fr) | 2010-03-03 | 2012-04-20 | Soitec Silicon On Insulator | Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante |
FR2955203B1 (fr) | 2010-01-14 | 2012-03-23 | Soitec Silicon On Insulator | Cellule memoire dont le canal traverse une couche dielectrique enterree |
FR2955200B1 (fr) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree |
FR2955195B1 (fr) | 2010-01-14 | 2012-03-09 | Soitec Silicon On Insulator | Dispositif de comparaison de donnees dans une memoire adressable par contenu sur seoi |
FR2955204B1 (fr) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Cellule memoire dram disposant d'un injecteur bipolaire vertical |
FR2957186B1 (fr) | 2010-03-08 | 2012-09-28 | Soitec Silicon On Insulator | Cellule memoire de type sram |
FR2957449B1 (fr) | 2010-03-11 | 2022-07-15 | S O I Tec Silicon On Insulator Tech | Micro-amplificateur de lecture pour memoire |
FR2958441B1 (fr) | 2010-04-02 | 2012-07-13 | Soitec Silicon On Insulator | Circuit pseudo-inverseur sur seoi |
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US6180487B1 (en) | 1999-10-25 | 2001-01-30 | Advanced Micro Devices, Inc. | Selective thinning of barrier oxide through masked SIMOX implant |
FR2804247B1 (fr) * | 2000-01-21 | 2002-04-12 | St Microelectronics Sa | Procede de realisation d'un transistor bipolaire a emetteur et base extrinseque auto-alignes |
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JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Soiウエーハの製造方法 |
KR100947815B1 (ko) * | 2003-02-19 | 2010-03-15 | 신에쯔 한도타이 가부시키가이샤 | Soi 웨이퍼의 제조 방법 및 soi 웨이퍼 |
US20050170570A1 (en) | 2004-01-30 | 2005-08-04 | International Business Machines Corporation | High electrical quality buried oxide in simox |
GB0411971D0 (en) * | 2004-05-28 | 2004-06-30 | Koninkl Philips Electronics Nv | Semiconductor device and method for manufacture |
JP4609026B2 (ja) * | 2004-10-06 | 2011-01-12 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US20060105559A1 (en) | 2004-11-15 | 2006-05-18 | International Business Machines Corporation | Ultrathin buried insulators in Si or Si-containing material |
US8138061B2 (en) * | 2005-01-07 | 2012-03-20 | International Business Machines Corporation | Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide |
US7217636B1 (en) | 2005-02-09 | 2007-05-15 | Translucent Inc. | Semiconductor-on-insulator silicon wafer |
JP2007080949A (ja) * | 2005-09-12 | 2007-03-29 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法 |
US8846549B2 (en) * | 2005-09-27 | 2014-09-30 | Macronix International Co., Ltd. | Method of forming bottom oxide for nitride flash memory |
JP2007103862A (ja) * | 2005-10-07 | 2007-04-19 | Renesas Technology Corp | 半導体装置およびその製造方法 |
FR2896618B1 (fr) * | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite |
FR2896619B1 (fr) | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite a proprietes electriques ameliorees |
JP2007227424A (ja) | 2006-02-21 | 2007-09-06 | Sumco Corp | Simoxウェーハの製造方法 |
EP2333824B1 (en) * | 2009-12-11 | 2014-04-16 | Soitec | Manufacture of thin SOI devices |
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JP2011512685A (ja) | 2011-04-21 |
DE112008003726T5 (de) | 2011-03-24 |
WO2009104060A1 (en) | 2009-08-27 |
US20100283118A1 (en) | 2010-11-11 |
US8148242B2 (en) | 2012-04-03 |
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