TWI437644B - Semiconductor substrate manufacturing method - Google Patents

Semiconductor substrate manufacturing method Download PDF

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TWI437644B
TWI437644B TW097140890A TW97140890A TWI437644B TW I437644 B TWI437644 B TW I437644B TW 097140890 A TW097140890 A TW 097140890A TW 97140890 A TW97140890 A TW 97140890A TW I437644 B TWI437644 B TW I437644B
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substrate
oxide film
film
soi
ion implantation
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TW097140890A
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TW200929385A (en
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Shoji Akiyama
Yoshihiro Kubota
Atsuo Ito
Makoto Kawai
Yuuji Tobisaka
Koichi Tanaka
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Shinetsu Chemical Co
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Description

半導體基板之製造方法
本發明，係有關於在透明絕緣性基板上具備有矽膜的半導體基板之製造方法。
作為能夠使半導體裝置高性能化之半導體基板，SOI(Silicon On Insulator)基板係受到注目(例如，參考專利文獻1或非專利文獻1)。此係因為，藉由採用SOI構造而在單結晶矽薄膜下埋入氧化膜，能夠減低寄生容量，提昇動作速度，而成為能夠抑制消耗電力之故。
當將SOI基板作為光裝置而利用的情況時，與矽基板作貼合之支持基板，係成為需要為透明絕緣性基板，但是，作為此種基板，除了石英基板或是藍寶石基板以外，從低成本化之觀點來看，硼矽酸玻璃基板或是結晶化玻璃基板等亦係被檢討。
但是，此些之透明絕緣性基板，由於其與矽結晶之熱膨脹係數係大為不同，因此，當SOI基板之製造工程中包含有高溫製程的情況時，會產生貼合基板或是SOI基板碎裂或是缺角等的問題。因此，係期望在SOI基板之製造工程全般中的低溫化，特別是，在將SOI膜形成於透明絕緣性基板上後之形成閘極氧化膜的工程中，係有必要達成低溫化。
於近年，作為代替需要高溫之熱氧化的低溫氧化技術，雖然亦提案有使用有高濃度臭氧之氧化法(非專利文獻2)、或是微波激勵電漿所致之氧化法(非專利文獻3)，但是，此些手法，係均需要與先前技術之裝置為相異的特殊之氧化系統。
[專利文獻1]日本專利第3048201號公報
[非專利文獻1]A. J. Auberton-Herve et al.,“SMART CUT TECHNOLOGY:INDUSTRIAL STATUS of SOI WAFER PRODUCTION and NEW MATERIAL DEVELOPMENTS”(Electrochemical Society Proceedings Volume 99-3(1999)p.93-106).
[非專利文獻2]黑河明他「藉由高濃度臭氧所形成之極薄氧化矽膜的界面構造」(電子技術總合研究所彙報，第63卷，第12號，p.501-507，2000年)
[非專利文獻3]大見忠弘他「微波激勵Kr/O2 電漿所致之氧化矽膜的低溫形成」『應用物理』(第69卷，第10號，p.1200-1204，2000年)
本發明，係有鑑於此種問題而進行者，其目的，係在於提供一種：具備有使用先前技術之一般性的氧化矽膜形成裝置而在低溫下所形成之閘極氧化膜的SOI基板。
為了解決此種課題，本發明之半導體基板之製造方法，其特徵為，具備有：在矽基板之主面上形成氫離子注入層之離子注入工程；和在透明絕緣性基板與前述矽基板之至少一方的主面上施加電漿處理之表面處理工程；和將前述透明絕緣性基板與前述矽基板之主面彼此作貼合之工程；和從前述貼合基板之前述矽基板而將矽薄膜機械性地剝離，而作成在前述透明絕緣性基板之主面上具備有矽膜之SOI基板之剝離工程；和將前述SOI基板之前述矽膜作平坦化處理之工程；和將前述平坦化後之矽膜表面以450℃以下之溫度來進行熱氧化而形成100以下的氧化膜之工程；和在前述熱氧化膜上藉由CVD法而堆積氧化膜並形成閘極氧化膜之工程。
前述CVD法所致之氧化，例如，係藉由N2 O與SiH4 之混合氣體、O2 與SiH4 之混合氣體、又或是TEOS氣體之至少一種的氣體而進行。
本發明之半導體基板之製造方法，係以更進而具備有：在前述CVD法所致之氧化膜的形成後，於以0.1～4莫耳%之濃度而包含有氫之惰性氣體氛圍中進行熱處理之工程為理想。
又，在前述剝離工程之前，係亦可具備有將前述貼合基板以100～300℃之溫度來進行熱處理之工程。
在本發明中所被使用之透明絕緣性基板，例如，係有石英基板、藍寶石基板、硼矽酸玻璃基板、又或是結晶化玻璃基板。
在本發明中，由於係將形成於SOI基板上之閘極氧化膜，設為將以450℃以下之溫度所成長之低溫熱氧化膜與CVD法所致之氧化膜作了層積者，因此，在藉由基底之熱氧化膜而使界面準位等之構造上的缺陷被作抑制的同時，經由被形成在該當熱氧化膜上之CVD氧化膜，而成為能夠對閘極氧化膜之厚度作調整。若藉由此種手法，則係成為能夠使用先前技術之一般性的氧化矽膜形成裝置來將閘極氧化膜作低溫形成，而能夠達成SOI基板製造製程之一貫性的低溫化。
以下，藉由實施例，對本發明之半導體基板之製造方法的實施形態作說明。另外，在以下之實施例中，雖係將石英基板作為透明絕緣性基板來作說明，但是，在本發明中所被使用之透明絕緣性基板，係亦可為藍寶石基板、硼矽酸玻璃基板、結晶化玻璃基板等。
[實施例]
圖1，係為用以說明本發明之半導體基板之製造方法的製程例之圖。於圖1(A)中所圖示的矽基板10，一般而言，係為單結晶Si基板，而支持基板，係為石英基板20。於此，單結晶Si基板10，例如，係為藉由CZ法(丘克拉斯基法)所育成之一般在市面上販售的Si基板，其導電型態或電阻率比等的電性特性值、或是結晶方位或結晶粒徑，係依存於藉由本發明之方法所製造的SOI基板所供以使用之裝置的設計值或是製程亦或是所製造之裝置的顯示面積等，而適宜地作選擇。另外，在此單結晶Si基板10之表面(貼合面)處，係亦可經由例如熱氧化等之方法而預先被形成有氧化膜。
被作貼合之單結晶Si基板10以及石英基板20的直徑係為相同，為了之後之裝置形成製程的便利，若是在石英基板20處亦設置與在單結晶Si基板10處所設置之定向平面(orientation flat，OF)相同之OF，並使此些之OF彼此合致而作貼合，則係為理想。
首先，在將Si基板10之溫度保持在不超過400℃之狀態(400℃以下)的條件下，在單結晶Si基板10之表面處注入氫離子(圖1(A))。此離子注入面，係成為之後的「接合面(貼合面)」。藉由氫離子注入，在單結晶Si基板10之表面近旁的特定之深度(平均離子注入深度L)處，係被形成有均一之離子注入層11(圖1(B))。若是將離子注入工程中之Si基板10的溫度保持在400℃以下，則係能夠顯著地對所謂「微共振腔(micro cavity)」的發生作抑制。另外，在本實施例中，氫離子注入時之單結晶Si基板10的溫度，係被設定為200℃以上400℃以下。
氫之離子注入時的劑量，係因應於SOI基板之規格等，而在例如1×1016 ～4×1017 atoms/cm2 的範圍內選擇適當之值。另外，根據先前技術，氫離子之劑量若是超過1×1017 atoms/cm2 ，則於其後所得到之SOI層表面會產生表面粗糙，故而，一般係設定為7×1016 atoms/cm2 左右的劑量。然而，若依據本發明者們之檢討，則係清楚得知了：在先前方法中被認定係會發生之於上述離子注入條件下所產生的SOI層之表面粗糙的原因，係並非在於氫離子之劑量本身，而係由於為了將矽薄膜剝離並得到SOI層所採用的較為高溫(例如500℃)之熱處理工程中所發生的氫的擴散現象之故。
故而，當如同本發明一般而達成了包含氫離子注入工程之一貫性的低溫製程化的情況時，不只是氫離子注入工程，連剝離工程亦係成為在低溫下實行，而能夠對該當剝離處理工程中之氫原子的擴散顯著地作抑制，因此，就算是施加高劑量之氫離子注入，亦不會產生SOI層之表面粗糙。本發明者們，雖係針對以各種之劑量來施加氫離子注入時的對於SOI層之表面粗糙的影響作了調查，但是，只要是藉由400℃以下之低溫熱處理來實行矽薄膜之剝離，則至少在直到4×1017 atoms/cm2 的劑量下，均無法發現表面粗糙的情形。
離子注入層11之從單結晶Si基板10表面起的深度(平均離子注入深度L)，係藉由離子注入時之加速電壓而被控制，並依存於欲將何種程度之厚度的SOI層作剝離一事而被決定，但是，例如，係將平均離子注入深度L設為0.5μm以下，並將加速電壓設為50～100keV等。另外，亦可如同在對於Si結晶中之離子注入製程時為了對注入離子之管道化(channelling)作抑制所通常進行一般，在單結晶Si基板10之離子注入面處預先形成氧化膜等之絕緣膜，並透過此絕緣膜而施加離子注入。
在此氫離子注入後，在單結晶Si基板10之接合面處，施加以表面清淨化或是表面活性化等為目的之電漿處理(圖1(C))。另外，此電漿處理，係為了將成為接合面之表面的有機物除去、或是使表面上之OH基增大而達成表面活性化等的目的所進行者，可以對單結晶Si基板10與石英基板20之雙方的接合面作施加，亦可僅對石英基板20之接合面作施加。亦即是，只要對單結晶Si基板10與石英基板20之任何一方的接合面作施加即可。
此電漿處理，係將預先被施加有RCA洗淨等之表面為清淨的單結晶Si基板以及/又或是石英基板載置在真空處理室內之試料台上，並在該當真空處理室內以使其成為特定之真空度的方式來導入電漿用氣體並實行。另外，作為於此所使用之電漿用氣體種，係有氧氣、氫氣、氬氣、又或是此些之混合氣體、或者是氫氣與氦氣之混合氣體等。在電漿用氣體之導入後，使100W左右之電力的高頻電漿產生，並在被作電漿處理之單結晶Si基板以及/又或是石英基板的表面處，施加5～10秒左右的處理，並結束之。
將被施加有此種表面處理後之單結晶Si基板10與石英基板20的表面作為接合面，並使其密著而作貼合(圖1(D))。如上述一般，單結晶Si基板10與石英基板20之至少一方的表面(接合面)，由於係藉由電漿處理而被施加有表面處理並被活性化，因此，就算是在室溫下而被作了密著(貼合)的狀態下，亦能夠得到足以承受在後面之工程中的機械性剝離或是機械研磨之等級的接合強度。
另外，接在圖1(D)之貼合工程之後，於剝離工程之前，亦可設置在將單結晶Si基板10與石英基板20相貼合後的狀態下，以100～300℃之溫度來進行熱處理的工程。此熱處理工程，係為以得到能夠提昇單結晶矽基板10與石英基板20間之接合強度的效果為主要目的者。
將此熱處理工程時之溫度設定為300℃以下的主要理由，除了防止上述之「微共振腔」的發生之外，亦考慮有由於單結晶矽與石英間之熱膨脹係數差與起因於該當熱膨脹係數差所造成的變形量、以及此變形量與單結晶矽基板10還有石英基板20之厚度。
另外，在此熱處理中，依存於氫離子之注入量，亦能夠期待有：使起因於單結晶Si基板10與石英基板20之兩基板間的熱膨脹係數差所造成的熱應力產生，而使離子注入層11內之矽原子的化學結合弱化的副效果。
接在此種處理之後，對被貼合後之基板以某些之手法來賦予外部衝擊而從單結晶矽之主體(bulk)來將矽膜機械性的剝離，而得到在石英基板20上具備有矽膜(SOI膜)12之半導體基板(SOI基板)(圖1(E))。另外，作為用以剝離矽膜(SOI膜)12之賦予從外部而來之衝擊的手法，係可採用各種之方法，但是，在本實施例中，此剝離係並不進行加熱地而實行。
在藉由原子力顯微鏡(AFM)而對如此這般所得到之SOI膜的剝離後之表面的10μm×10μm之區域作了測定後，RMS之平均值係為5nm以下，而為良好。又，SOI膜之基板面內誤差(PV)，係為4nm以下。能夠得到此種較為平滑之剝離面的理由，係由於此剝離機制係與先前技術之熱剝離為相異之故。
所得到之SOI基板的表面(SOI膜表面)，係被施加CMP研磨而被平坦化，並更進而被洗淨而成為清淨面。
本發明之SOI基板，係具備有閘極氧化膜，該當氧化膜，係藉由下述之2個的工程而形成。首先，將SOI膜12之清淨面以450℃以下之低溫度來進行熱氧化，並形成100以下之薄的基底熱氧化膜13(圖1(F))。一般之熱氧化膜，係需要900℃以上之溫度，但是，在本發明中，由於熱氧化膜13係為100以下之薄膜，因此，就算是450℃以下之低溫，亦係為充分。例如，當在450℃而藉由乾氧化法來進行了12小時之熱氧化的情況時，係可得到85之熱氧化膜。
接下來，在熱氧化膜13之上，藉由CVD法，而以600℃以下之溫度來更進而堆積氧化膜14(圖1(G))。此氧化膜14與熱氧化膜13，係成為閘極氧化膜。作為CVD法所致之氧化用氣體，例如，係可使用N2 O與SiH4 之混合氣體、O2 與SiH4 之混合氣體、又或是TEOS氣體等。
此種構造之閘極氧化膜，係具備有以下之優點：在藉由基底之熱氧化膜13而使界面準位等之構造上的缺陷被作抑制的同時，經由被形成在該當熱氧化膜上之CVD氧化膜14，而成為能夠進行厚度之調整。藉由採用此種氧化手法，在能夠得到最適當之閘極氧化膜厚的同時，由於閘極氧化膜之形成製程係成為一貫化地以低溫來實行，因此，成為能夠對由熱膨脹率相異之材料所成的複合基板(在石英基板、藍寶石基板、硼矽酸玻璃基板、又或是結晶化玻璃基板上具備有矽膜之基板)之矽膜中的結晶缺陷之發生作抑制。
另外，以將熱氧化膜13以及CVD氧化膜14中之構造性缺陷作電性的惰性化一事為目的，亦可在CVD氧化膜14的形成後，更進而設置於以0.1～4莫耳%之濃度而包含有氫之惰性化氣體氛圍中進行熱處理之工程。反應速度，由於基本上係與氫之分壓成比例，因此，對於氫濃度，基本上係並沒有下限(只要將氧化時間延長即可)，但是，現實而言，係期望為0.1莫耳%以上。關於上限，係以爆發界限(氫濃度4莫耳%以下)的組成氣體，在處理上較為容易。
 [產業上之利用可能性]
藉由本發明，係成為能夠使用先前技術之一般性的氧化矽膜形成裝置來將閘極氧化膜作低溫形成，而能夠達成SOI基板製造製程之一貫性的低溫化。
10．．．矽基板
11．．．離子注入層
12．．．矽膜(SOI膜)
13．．．熱氧化膜
14．．．CVD氧化膜
20．．．石英基板
[圖1]用以說明本發明之半導體基板之製造方法的製程例之圖。
10．．．矽基板
11．．．離子注入層
12．．．矽膜(SOI膜)
13．．．熱氧化膜
14．．．CVD氧化膜
20．．．石英基板

Claims (5)

  1. 一種半導體基板之製造方法，其特徵為，具備有：在矽基板之主面上形成氫離子注入層之離子注入工程；和在透明絕緣性基板與前述矽基板之至少一方的主面上施加電漿處理之表面處理工程；和將前述透明絕緣性基板與前述矽基板之主面彼此作貼合而作成貼合基板之工程；和從前述貼合基板之前述矽基板而將矽薄膜機械性地剝離，而作成在前述透明絕緣性基板之主面上具備有矽膜之SOI基板之剝離工程；和將前述SOI基板之前述矽膜作平坦化處理之工程；和將前述平坦化後之矽膜表面以450℃以下之溫度來進行熱氧化而形成100Å以下的熱氧化膜之工程；和在前述熱氧化膜上藉由CVD法而堆積氧化膜並形成閘極氧化膜之工程。
  2. 如申請專利範圍第1項所記載之半導體基板之製造方法，其中，前述CVD法所致之氧化，係藉由N2 O與SiH4 之混合氣體、O2 與SiH4 之混合氣體、又或是TEOS氣體之至少一種的氣體而進行。
  3. 如申請專利範圍第1項或第2項所記載之半導體基板之製造方法，其中，係更進而具備有：在前述CVD法所致之氧化膜的形成後，於以0.1~4莫耳%之濃度而 包含有氫之惰性氣體氛圍中進行熱處理之工程。
  4. 如申請專利範圍第1項或第2項所記載之半導體基板之製造方法，其中，在前述剝離工程之前，係具備有將前述貼合基板以100~300℃之溫度來進行熱處理之工程。
  5. 如申請專利範圍第1項或第2項所記載之半導體基板之製造方法，其中，前述透明絕緣性基板，係為石英基板、藍寶石基板、硼矽酸玻璃基板、又或是結晶化玻璃基板之任一者。
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