WO2009128776A1

WO2009128776A1 - Hybrid wafers with hybrid-oriented layer

Info

Publication number: WO2009128776A1
Application number: PCT/SE2009/050385
Authority: WO
Inventors: Örjan Vallin; Sören Berg; Jörgen OLSSON; Ulf Smith; Ling-Guang Li; Hans NORSTRÖM
Original assignee: Vallin Oerjan; Berg Soeren; Olsson Joergen; Ulf Smith; Ling-Guang Li; Norstroem Hans
Priority date: 2008-04-15
Filing date: 2009-04-15
Publication date: 2009-10-22

Abstract

The present invention provides a hybrid wafer with a hybrid-oriented surface layer on a high thermal conductivity layer (10). The hybrid-oriented layer comprises at least a first single-crystal SixGei-x layer (15) and a second single-crystal SixGei-x layer (117), optionally with an intermediate layer (21) having a thickness of between 1 nanometer and 1 micrometer and comprising at least one amorphous or polycrystalline SixGei-x layer. Thanks to the invention it is possible to integrate components made from different materials, using combinations like, e.g., Si-GaAs, Si- GaN and Si-SiC, and p-MOS and n-MOS transistors on one single IC chip. Further it is possible to improve electrical and thermal performances of such hybrid circuits.

Description

HYBRID WAFERS WITH HYBRID-ORIENTED LAYER

TECHNICAL FIELD

The invention relates generally to wafers for production of integrated circuits and, more specifically, to hybrid wafers having hybrid silicon crystalline layers.

BACKGROUND OF THE INVENTION

It is well known in the field of integrated circuit (IC) technology that the mobility of the charge carriers in a p-MOS (Metal Oxide Semiconductor) transistor, i.e. the holes, suffers when the transistors are made in (lOO)-surface orientated silicon wafers, as is commonly the case. The hole mobility will only be approximately half of that for the electrons, the latter constituting the charge carriers in an n-MOS transistor. This will require larger p-MOS transistors so that they can balance the performance of the n-MOS transistors in an integrated circuit. As a consequence, there will be a detrimental increase in gate- and other parasitic-capacitances in the p-MOS transistor.

A low hole mobility will also have direct impact on the on-resistance and the peak drive-current in the p-MOS transistor. An improved mobility will also lead to higher values for the characteristic frequencies Ft and Fmax for the transistor. These parameters are all of paramount importance when designing Laterally Diffused Metal Oxide Semiconductor (LDMOS) ICs for radio frequency (RF) power applications, since the have direct influence on the performance of the circuit.

One way to improve the hole mobility is to selectively change the crystallographic orientation of the p-MOS transistor channel from traditionally <110> to <100>, but this will only lead to a marginal increase.

A much larger improvement can, however, be achieved if the surface orientation of the silicon wafer is selected to be (110) instead of the more common (100). Transistors made on such an (110)-oriented surface and with the channel aligned in the <110> direction can achieve mobility values twice those on a (lOO)-oriented surface. The shortcoming of this is, however, that wafers with a (110)-oriented surface are not suitable for high-performance n-MOS transistors. Consequently, there is a need to work with wafers having discrete areas with (100) and (110) orientations on one and the same wafer so as to allow individual optimisation of the n- and p- MOS transistors respectively.

The electrical problem presented above has been discussed extensively in a paper by Min Yang et al. entitled "Hybrid-Orientation Technology (HOT): Opportunities and Challenges", /EEE Transactions on Electron Devices, Vol. 53, No. 5, May 2006, pp. 965-78. This paper discloses an all-silicon hybrid-orientation technology that provides nFΕTs (Field-Effect Transistor) on (100) surface orientation and pFETs on (110) surface orientation through wafer bonding and selective silicon epitaxy.

In addition to the electrical problem just described, the limited thermal conductivity of silicon (Si) can cause overheating problems when high-power components are present in an integrated circuit. As a consequence, Si components cannot be close-packed to extents that would be desirable from performance and economical points of view. The poor thermal conductivity of Si also puts limits on the power permitted in discrete Si components. The only way to circumvent these limits is to resort to advanced cooling methods. Examples of applications where the limited thermal conductivity forms a serious obstacle to further technical development are power modules in communication systems for mobile telephony, broadcasting, as well as transmitter modules in radar systems.

The problem grows even worse if the components have to be electrically insulated from the substrate. This is usually achieved by means of an intermediate layer of silicon dioxide (SiO₂). However, the thermal conductivity of such a layer is 100 times worse than that of Si. An example of such insulation is the commercially available hybrid wafer "Silicon-on- Insulator" (SOI), where a crystalline layer of Si is insulated from the underlying Si wafer by a layer of SiO₂. The problem with a limited thermal conductivity can be solved to some extent if a wafer made from the insulator sapphire is used, since the thermal conductivity of sapphire is almost 25 times that of SiO₂. The single-crystal Si layer is grown directly on the sapphire to form the commercially available "Silicon-on-Sapphire" (SOS) wafer. However, a large part of the thermal transport problem remains, since the sapphire has to be made quite thick in order to provide the necessary mechanical strength. Thus the increase in thermal conductivity is negated by a longer path for the heat transport. As a consequence, SOS wafers will not be able to satisfy the steadily rising demands for increased performance. Furthermore, the electrical properties of the Si layer grown on the surface of the SOS wafer are inferior to those of bulk Si. Having the bulk of the wafer made of an insulator also poses the limitation that semiconductor components cannot be integrated in the SOS wafer itself, in contrast to the situation for SOI wafers. In the latter case, a removal of the Si-layers and the SiO₂-layers in selected areas makes it possible to have components in the Si layer and the Si substrate on the same chip. The component parts of an IC can then be designed into whatever area that guarantees the best performance.

Wafers and components made from silicon carbide (SiC), on the other hand, are known to have good high-voltage, high-frequency and thermal-conductivity properties. However, serious limitations exist with regard to the manufacture of ICs in this material due to the fact that the number of components that can possibly be included is presently limited. Furthermore, standardized methods for an industrial manufacture of SiC ICs are not yet available in contrast to the situation for Si wafers.

As of today, SiC wafers of acceptable quality can only be manufactured with the help of very costly processes. This is related to the fact that most known processes give rise to large numbers of "pipes" in the material. Such defects have serious consequences for the electrical properties of the material and must therefore be avoided. Prime wafers of SiC are consequently quite expensive, which makes it desirable to try to limit the amount of material needed for the manufacture of SiC components as much as possible. Attempts have been made to achieve this by bonding a thin layer of SiC to a bulk Si wafer (Tong, Q.-Y. Lee, T.-H., Huang, L.-J., Chao, Y.-L. and Gδsele, U. "Si and SiC layer transfer by high temperature hydrogen implantation and lower temperature layer splitting", Electronics Letters, v. 34, nr 4, (1998), p 407-8). Although this makes it possible to take advantage of the excellent electrical properties of the SiC without an excessive consumption of material, the limited thermal conductivity of the Si substrate still poses a serious problem. Another way of limiting the amount of material used is to use wafers with small diameters, such as 2" or 3 " wafers. However, serious limitations then arise in connection with the manufacture of components, since commercial production equipment is no longer available for such small diameters.

Attempts to solve the abovementioned problems are known. Thus, a thin layer of crystalline Si attached to an SiC wafer, either directly or with an intermediate layer of e.g. Si, silicon dioxide or diamond has been described in US Patent Nos. 6,521,923 and 6,497,763 as well as in an article in Compound Semiconductor, Nov. 2005, pp 24-6. The single-crystal Si layer can be nominally stress-free or it can be under stress. Although poly-Si was used as a possible intermediate layer when bonding the single-crystal Si layer to the SiC wafer, this was only made in order to simplify a previous planarization of the surface of the SiC wafer. The reason for this is that SiC is extremely hard and therefore difficult to polish, whereas Si is soft enough to give a surface perfect for bonding after, for example, Chemical Mechanical Polishing (CMP).

SiO₂ has also been used as a planarizable intermediate layer in connection with the bonding of a single-crystal Si layer to an SiC wafer. Although the SiC substrate itself is a good heat conductor, such an intermediate layer bring back the heat-flow problem, since SiO₂ is such a poor heat conductor that already a thin layer will severely negate the good heat conductivity of the substrate.

A direct conflict between the requirements for optimum electrical and thermal performances, respectively, is seen with regard to materials for high-power RF circuits, where losses due to the electromagnetic fields constitute a very serious problem. The capacitive coupling between the conductors and the substrate will give rise to severe reductions in the useful signal unless high- ohmic Si substrates are used. Likewise, there will be serious loss of useful power due to the resistive losses generated by the induced substrate currents. To some extent, it has been possible to limit these losses in Si substrates by the use of SOI wafers. But the SiO₂ layer present in the SOI wafers will, as mentioned above, severely obstruct the flow of heat from component to substrate. Although the heat-flow problem can be solved by building the RF components in the abovementioned Si-SiC combination, such a solution alone is not electrically ideal. Numerous attempts have been made to solve the critical electrical-optimization problem for RF components. However, they all suffer from the lack of a simultaneous optimization of the thermal problems, hi the case of RF components made from, e.g., GaAs, InP and GaN, it is quite common to isolate the active components from each other by removing the surrounding material by means of etching. The components thus appear in the form of mesas distributed over the chip surface. Techniques exist where the capacitive coupling to the substrate is reduced by having the electrical conductors run between the mesas in the form of air bridges with no dielectric under. Another example of the use of air-bridges is for RF heterojunction bipolar transistors in silicon- germanium. It is clear that the introduction of such bridging-type connections leads to a substantially more complicated manufacturing process. Isolation of components by forming mesas is also used for components in SOI wafers, where trenches through the silicon layer and down to the buried oxide layer surround the mesas. However, the oxide under the mesas gives rise to the usual problems with adequate heat removal.

The fact that one goes to such extremes as to use electrical conductors in the form of bridges illustrates how important the design of the conductors is for the performance of the circuit. In order to obtain interconnects with low attenuation, it is common to use a thick insulator between the silicon substrate and the metal layers above. Sufficiently thick insulating layers cannot always be manufactured from SiO₂, however. Instead, one has to resort to polymers like polyimide, which introduces additional complexity into the production process. Another means of obtaining low attenuation is to use a conducting ground-plane in the form of a highly doped substrate or a buried metal layer. Although simpler to implement than air-bridges, these solutions also introduce a substantial complexity into the manufacturing process.

As an example of commercially available components suffering from problems regarding insufficient heat removal as well as excessive resistive and capacitive losses in the conductors, LDMOS are mentioned. There are companies that manufacture their LDMOS circuits in epitaxial layers on highly doped bulk-silicon substrates using conventional IC design and manufacturing methods. Attempts to improve the situation have been made in that SOI substrates have been used. The underlying bulk substrate has then been low-to-medium doped with resistivities in the range 10 - 10³ ohmcm. However, serious problems then arise in that the substrate under the buried oxide layer can be influenced by charged carrier traps at the interface between the buried oxide layer and bulk silicon substrate, if not by the bias potentials applied to the components. Unintended inversion, depletion or accumulation can then take place in the surface region of the bulk substrate. This will, among other things, influence the efficiency of the LDMOS substantially. It has recently been shown that if the silicon substrate in the SOI wafer is given a low resistivity, the RF efficiency is drastically improved (Ref: J. Ankarcrona et al, "Low Resistivity SOI for Improved Efficiency of LDMOS", Proc. EUROSOI Workshop, pp. 69-70 (March 2006)). The high doping level of the substrate eliminates the above-mentioned inversion, depletion or accumulation at the interface. However, this only works for certain specific combinations of doping levels in the LDMOS transistor itself. The problems associated with the poor heat-conduction of SiO₂ remain. As to integration of components made from different materials on one single IC chip, using combinations like, e.g., Si-GaAs, Si-GaN and Si-SiC, no applications of any type are known as of today.

SUMMARY OF THE INVENTION

The object of the invention is to solve the problems and shortcomings discussed above.

This is attained by a first aspect of the invention which is directed to a hybrid wafer comprising a hybrid-oriented surface layer on a high thermal conductivity layer. The hybrid-oriented surface layer comprises at least a first single-crystal Si_xGe_1-x layer, where 0 < x < 1, and a second single- crystal Si_xGe_1-x layer (117), where 0 < x <1, wherein the first and the second single-crystal SiχGe_1-x layers have different surface orientation.

In one embodiment of the invention the hybrid wafer further comprises, between the first single- crystal Si_xGei_-x layer and the high thermal conductivity layer, an intermediate layer comprising at least one amorphous or polycrystalline Si_xGe_1-x layer, where 0 ≤ x <1. Hence this layer is in the following for simplicity referred to as a poly-Si layer. In one embodiment of the invention poly-Si layer is doped with fluorine in order to obtain defect passivation.

The hybrid wafer may during the manufacturing process be thermally oxidized to create an interfacial thin oxide layer between said single-crystal Si_xGe_{1 -x} layers. This may later on in the process serve as an etch stop and it is made so thin that it can be dissolved during a final heat treatment.

The hybrid-oriented surface layer may further comprise a third single-crystal Si_xGe_{1 -x} layer, where 0 < x < 1, the surface orientation of the third single-crystal Si_xGe_1-x layer is different from the surface orientation of the first and the second single-crystal Si_xGe_1-x layers. The single- crystal Si_xGe_1-x layers may have any suitable surface orientation, including those of (100), (110) and (111). In a second aspect of the invention a method for manufacturing a hybrid wafer comprising a hybrid-oriented surface layer on a high thermal conductivity layer is provided. The method comprises the steps of bonding at least a first and a second single-crystal Si_xGe_1-x layer on a high thermal conductivity layer. The method may further comprise the steps of oxidizing the first single-crystal Si_xGei_-x layer in order to form an interfacial oxide layer for the bonding and later in the process heat treating the hybrid wafer in order to dissolve the oxide layer.

Thanks to the invention it is possible to integrate components made from different materials, using combinations like, e.g., Si-GaAs, Si-GaN and Si-SiC, and p-MOS and n-MOS transistors on one single IC chip.

It is a further advantage of the invention to provide improved electrical and thermal performances of such hybrid circuits.

Embodiments of the invention are defined in the dependent claims. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described more in detail below with reference to the appended drawing on which

FIG. 1 depicts part of one embodiment of the present invention involving the manufacture of a hybrid wafer, FIG. 2 shows an embodiment of a hybrid wafer,

FIGs 3A-3F illustrate the utilization of the hybrid wafer in the manufacture of a wafer with a hybrid-oriented Si_xGe i_-x surface layer containing regions with the surface orientations (100) and

(110),

FIG. 4 schematically illustrates one embodiment of a hybrid wafer comprising three differently oriented Si_xGe_1-x surface layers,

FIG. 5A-5B depicts one embodiment of the present invention involving the actual manufacture of IC components in the Si_xGe_{1 -x} layer and in the SiC wafer,

FIG. 6 illustrates the utilization of the hybrid wafer according to the invention for an additional integration of IC components of materials from the III- V groups in the periodic table, ^" FIG. 7 illustrates the addition of GaN components in a grown GaN layer, and FIG. 8 schematically illustrates one embodiment of a method of manufacturing a hybrid wafer according to the present invention.

DESCRIPTION OF THE INVENTION

In order to provide the necessary background, the description of embodiments covered by the invention begins with a brief description of methods that can be used to substantiate such an invention.

A brief description is first given of methods for making hybrid wafers consisting of mono- crystalline layers of Si having hybrid orientations and being bonded to a carrier wafer having high thermal conductivity.

As an example, the starting material for the carrier wafer can be mono- or poly-crystalline SiC. A thin single-crystal layer with (100) surface orientation is transferred to the carrier wafer by means of wafer bonding in a manner described in more detail below. This hybrid substrate material is thermally oxidized in order to create a thin layer of SiO₂ on the Si surface. This thin layer will later in the process serve as an etch stop when a second Si layer is patterned. The thickness of the oxide layer is deliberately made so thin that it can later be dissolved in a heat treatment at high temperature. Typical values for the oxide thickness lie in the range 0.5 to 500 nm, preferably 0.5 to 50 run. With an annealing temperature in the range 1050 to 1300⁰C, preferably 1150 to 1250⁰C such an oxide thickness will remain for 10 min up to a few hours. Following oxidation, a second single-crystal Si layer, this time with a different surface orientation, namely (110), is wafer bonded on top of the thin layer of SiO₂. The well-known layer transfer technique SmartCut can be used for this purpose. The wafer is orientated so as to align its <110> crystal direction with the <110> direction in the already bonded and oxidized layer. This will ensure that the gates of n- and p-MOS transistors can have the same parallel orientation. The bonding interface is subsequently strengthened by a high-temperature annealing step. The temperature is selected as above so that it will not lead to the oxide interface being prematurely dissolved in the surrounding Si layers. The composite wafer is then lithographically patterned to define areas for n-MOS transistors. In this step, the (110)-oriented second Si layer is removed by dry etching in those areas where the n-MOS transistors are to be manufactured. The interfacial oxide acts as an etch stop in this step. The thin oxide layer in the opened areas is subsequently removed by wet etching. The wafers are annealed at high temperature prior to further processing in order for the interface oxide to dissolve. After annealing, a silicon layer is grown on the thus prepared wafer surface. This is preferably done by means of an epitaxial growth process during which the added silicon atoms orient themselves according to the (100) orientation in the opened areas. Epitaxial growth processes are well known amongst persons active in the field. The result after the epitaxial process is a hybrid silicon layer with areas having (100) orientation next to areas with (111) orientation. To compensate for different growth rates in differently oriented areas, the surface of the final wafer is chemically-mechanically polished (CMP) after epitaxy. Any dislocations occurring at an intersection of the two areas having different crystal orientations will not constitute a problem, since these areas will be oxide isolated by means of surrounding trenches and will also be placed far from the active component areas.

As another example, a hybrid wafer with hybrid-oriented layers is provided in manner analogous to that described above, by transferring a thin single-crystal Si layer with (111) surface orientation to the carrier wafer by means of wafer bonding. Following thermal oxidization in order to create a thin oxide layer, a second single-crystal Si layer, this time with a different surface orientation, namely (100) or (110), is wafer bonded on top of the thin oxide layer. The bonding interface is subsequently strengthened by a high-temperature annealing step. The (100)- oriented or (110)-oriented second Si layer is selectively removed by dry etching in predetermined areas where the components are to be manufactured using the interfacial oxide layer as an etch stop. The processing then continues as in the case of the hybrid wafer with hybrid-oriented layers above.

As yet another example, a hybrid wafer with three hybrid-oriented layers is provided in a manner analogous to the examples above. A first mono-crystalline Si layer with (111) surface orientation is transferred to the carrier wafer by means of wafer bonding, followed by thermal oxidization in order to create a first thin layer of SiO₂ on the Si (111) surface. Thereafter, a second single- crystal Si layer with (100) surface orientation is wafer bonded on top of the first thin oxide layer, followed by thermal oxidization in order to create a second thin layer of SiO₂ on the Si (100) surface. In the next step, a third single-crystal Si layer with (110) surface orientation is wafer bonded on top of the first thin oxide layer. The further processing may comprise the step selectively removing one or more of the first, second and third single-crystal layers to expose the underlying carrier wafer, the single-crystal Si layer with (111) surface orientation and the single- crystal Si layer with (100) surface orientation, respectively. This will enable parallel orientation of the gates of the n- and p-MOS transistors by utilizing the single-crystal Si layers with (100) and (110) orientations as discussed above. In addition, the single-crystal Si layer with (111) orientation can be utilized for other purposes, such as for epitaxial growth of III- V materials. The processing then continues as in the cases of hybrid wafers with hybrid-oriented layers above.

The term wafer originates from the fact that when manufacturing electronic devices silicon wafers, or as described in this application from SiC wafers or the like, are used as a starting point for further processing. However for the purpose of this application the term wafer is not limited to being a starting point but refers to electronic substrates in general, which may form at least part of a starting wafer for further processing or an intermediate or final product.

A brief description is now given of methods for making hybrid wafers consisting of mono- crystalline Si on SiC.

As an example, a high thermal conductivity layer or wafer, e.g. a silicon carbide (SiC) wafer, is chosen as the starting point. Not only prime single-crystal SiC wafers can be used, but also seconds, polycrystalline and sintered wafers. Apart from the apparent cost savings, this imparts flexibility in that wafer sizes compatible with current IC-processing equipment can be used.

If so desired, the otherwise excellent heat conduction properties of the SiC wafer can at this stage be enhanced by a diamond-like coating. Such a coating has a heat conductivity that is typically 4 - 5 times that of the SiC wafer. It will therefore not only provide an easy path into the SiC wafer for the heat generated by electrical components, but will also facilitate a rapid lateral spreading of the heat. The diamond layer thereby smoothes out local peaks in the heat-distribution, if such peaks are present due to some components having an exceptionally high power-dissipation.

That surface of the SiC wafer or the composite diamond-coated SiC wafer, as the case may be, which is to be bonded to a transferred Si layer is first coated with an Si layer consisting of polycrystalline or, preferably, amorphous Si. This layer will for simplicity be referred to as a poly-Si layer. The layer can be deposited by means of, for example, Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD). The poly-Si layer is prepared for its intended final use by the implantation of dopant atoms. In cases where the poly-Si layer is to have n-type conduction, the implanted atoms can be any one or all of phosphorus (P), arsenic (As) or antimony (Sb). If p-type conduction is preferred, the implanted atoms can be any one or all of boron (B), aluminum (Al), gallium (Ga) or indium (In). Alternatively, the dopant atoms can be introduced in situ, i.e. concurrently with the deposition of the poly-Si layer. In all cases, the preferred level of doping is so large that it will lead to a degenerate or almost degenerate gas of charge carriers in the poly-Si layer after completed processing. Such preferred carrier concentrations fall in the range 10¹⁸ - 10²⁰ cm^"3. However, as will be clear from the over-all description of the hybrid wafer, it does not exclude lower doping levels, or even undoped poly- Si. The poly-Si layer can also be doped with fluorine (F) in order to obtain defect passivation. The fluorine attaches to dangling silicon bonds present at the grain boundaries and thereby passivates the dangling bonds. This prevents the dangling bonds from acting as traps for the carriers, a process which would otherwise remove carriers from the conduction process. The electric charge of the trapped carriers at the dangling bonds can also interfere destructively with the operation of the devices in the silicon layers. The doped poly-Si layer can be thermally activated at this stage or at a later stage. The surface of the poly-Si layer can be planarized, e.g. by means of CMP, to a Root Mean Square (RMS) smoothness of preferably not more that 10 A. This can be done before as well as after the introduction of the dopant in the poly-Si layer

The CMP step takes advantage of the mechanical properties of the poly-Si layer compared to those of the underlying SiC surface. The limited hardness of the poly-Si layer makes it much easier to polish than the extremely hard SiC surface.

A handle wafer to be used in the layer transfer process consists of an Si wafer prepared to a quality level representative of standard semiconductor manufacturing, but with a front surface that has an RMS smoothness of, preferably, 10 A. The surface of the wafer can, if necessary, have a poly-Si layer similar to that on the surface of the SiC wafer. An Si layer of the required thickness can be separated from the Si handle wafer in many ways. One is to use the so called "Smart Cut" method. In this case, the wafer is further prepared by implanting hydrogen ions through the front surface to a depth which defines the thickness of the Si layer to be transferred. As an alternative to this, the thickness of the Si layer to be transferred is defined by means of the formation of an etch- stop layer inside the handle wafer. Such an etch-stop layer can consist of a crystalline layer of silicon-germanium (SiGe), on top of which the single-crystal Si layer has been grown. Still another alternative is to use the buried oxide layer in an SOI wafer as the etch- stop layer. From this it follows that the transferred layer can also be under mechanical strain. Typical Si layer thicknesses fall in the range 0.01 - 10 μm. The prepared surface of the handle wafer is placed in contact with the prepared surface of the SiC wafer. If the preparations are properly done, the two surfaces will adhere to each other instantaneously. The two wafers can also be pressed together if deemed necessary. The two- wafer package is then subjected to a judiciously selected heating cycle that will cause: 1) a splitting-off of the Si layer from the handle wafer if the SmartCut method is to be used, 2) an increase in the strength of the atomic bonding of the two surfaces, 3) a transformation of the poly-Si layer to a recrystallized layer with slightly or largely increased grain sizes with defects suitable for impurity gettering and 4) an activation of the dopant atoms in the recrystallized poly- Si layer. The heat treatment is best accomplished by means of Rapid Thermal Annealing (RTA). Typical temperatures for steps 2 to 4 fall in the range 900 - 1100 °C. The heating cycle can also be performed in a furnace at a single temperature, or by means of a series of consecutive temperature steps. Preferred temperatures and times for these steps fall in the range 600 - 1100 °C and 80 - 20 min. It is important to select the parameters for the thermal treatment in such a way that the original poly- Si layer recrystallizes into a large-crystal layer with plenty of defects localized inside the grains for optimum gettering performance. It was discovered that, with a judicious choice of the thermal treatment procedure, the formation of a recrystallized layer with such properties is facilitated by the stresses within the poly-Si layer during the thermal treatment. These stresses arise due to the fact that the poly-Si layer is confined between two rigid surfaces, namely that of the handle wafer and that of the SiC wafer.

It follows from the description above that either one or both of the surfaces that are to be bonded together can be coated with an Si layer consisting of polycrystalline or, preferably, amorphous Si, also referred to as "poly-Si" above for simplicity. After bonding, said poly-Si layer or layers, as the case may thus be, forms or form an intermediate poly-Si layer at the interface between the SiC wafer, or the composite diamond-coated SiC wafer as the case may be, and the Si layer.

The above-mentioned gettering effect of the recrystallized layer will manifest itself during the process of manufacturing of IC components. Inevitable impurity atoms that are introduced in the single-crystal device layer during processing will during the heat treatments migrate down to and bind with the local defects in the recrystallized layer. There, the impurity will be out of harm's way with respect to the vital parts of the IC components in the surface. In the absence of such intentionally generated gettering sites, the impurity atoms will most likely collect at the interfaces of the parts that make up the IC components. In cases other than that of the SniartCut method, the bulk of the handle wafer and the etch-stop layer are removed by means of selective etching. Finally, the surface of the transferred single- crystal Si layer can be polished by means of CMP to a smoothness appropriate for subsequent semiconductor processing. The hybrid wafer is now ready for the manufacture of components.

A slightly different method will be necessary if a hybrid device Si layer consisting of two or more single-crystal Si layers having different surface orientations, and containing processed IC components is to be transferred from a Si-based wafer on to, e.g., a SiC substrate in order to form a hybrid wafer. In this case, the surface of the processed IC wafer is attached to a wafer that is to serve as a temporary handle wafer by means of a suitable polymer, e.g. a photoresist. The processed IC wafer is then thinned from the back side by means of mechanical grinding combined with a chemical etch or a plasma etch down to a built-in etch-stop layer in the processed IC wafer. Such an etch-stop layer can consist of a crystalline layer of silicon- germanium (SiGe) on top of which a single-crystal Si layer has been grown before the start of the IC process. Still another alternative is to use the bulk oxide layer of an SOI wafer as the etch- stop layer. Typical single-crystal Si layer thicknesses fall in the range 0.01 - 10 μm. The layer surface of the so prepared temporary handle wafer with the attached single-crystal Si layer is then placed in contact with the surface of the SiC wafer. As was the case above, either one or both surfaces can have a coating of poly-Si as a part of the surface preparation. If properly prepared, the two surfaces will adhere to each other instantaneously. The two wafers can also be pressed together if deemed necessary. The two-wafer package can then be subjected to a judiciously selected heating cycle in order to increase the strength of the atomic bonding of the two surfaces. The handle wafer is then separated from the device layer containing the processed IC components by chemical dissolution of the polymer. Additional heating can then be used for optimization of the bond strength as well as the properties of the intermediate layer.

This exemplifies the major steps in the realization of a hybrid wafer with an optimized recrystallized poly-Si interface.

Unlike the case just mentioned, with hybrid wafers having a hybrid-oriented device layer containing processed IC components, components now have to be manufactured in the single- crystal hybrid-oriented Si layer. When this has been done, the continued processing of the two types of hybrid wafers is the same. Although the above description of the making of hybrid wafers concentrated on SiC wafers, it should be pointed out that other wafer materials showing high thermal conductivity can also be used. Examples are wafers made from Group III nitrides, i.e. AlN, GaN and InN. Another example is wafers made of diamond. As was the case with the SiC wafers, prime single-crystal, seconds, polycrystalline and sintered wafers can be used in the form of pure compounds or mixtures. A recent reference to the literature is: L. J. Showalter et al, "Fabrication of Native Single-Crystal AlN Substrates", Proc 21st Century COE Joint Workshop on Bulk Nitrides, IPAP Conf. Series 4, pp. 38-40 (June 2004).

The description above of a possible realization of a hybrid wafer referred to crystalline layers and handle wafers consisting of Si. It should be clear, however, that this implies no limitation, since, more generally, Si_xGe_{1 -x} with 0 = x = 1, or any other material that commonly is used for these purposes, can be used.

In order to introduce concepts used for further illustration, the abovementioned general description will now be detailed with the help of FIG. IA and FIG. IB.

As starting point an SiC wafer 10 is chosen, for which any one or a combination of the following alternatives exist: a prime or second quality single-crystal SiC wafer of any one of the crystallographic types 4H, 6H or 3 C, a prime or second quality polycrystalline SiC wafer, a prime or second quality single-crystal SiC wafer of any one of the crystallographic types 4H, 6H or 3 C coated with a diamond-like layer 11, a prime or second quality polycrystalline SiC wafer coated with a diamond-like layer 11. Typical thicknesses for the diamond-like layer 11 fall in the range 1 - 10 μm. The SiC wafer 10, with or without the diamond-like layer 11, is coated with a layer 12 of polycrystalline or, preferably, amorphous Si. This layer will in the following be denoted poly-Si layer 12 for brevity. The polycrystalline or amorphous Si layer can be deposited by means of CVD or PVD. If so desired, dopant atoms can be added in connection with the deposition process. Typical thicknesses and dopant concentrations for poly-Si layer 12 fall in the ranges 0.01-10 μm and 10¹⁸ - 10²⁰ cm^"3, respectively. The poly-Si layer 12 can also be left undoped.

The other starting point is a handle wafer 16. Handle wafer 16 has at least a surface layer 15 of appropriate thickness consisting of single-crystal Si with electrical and mechanical properties typical for semiconductor manufacturing. For further enhancement of the properties, surface layer 15 can be coated with a layer 13 of polycrystalline or, preferably, amorphous Si. This layer will in the following be denoted poly-Si layer 13 for brevity. Poly-Si layer 13 is deposited by the same methods as, and has properties similar but not necessarily equal to, those of poly-Si layer 12. The surface layer 15 on handle wafer 16 which will form the single-crystal Si surface-layer in the finished hybrid wafer is for brevity referred to as single-crystal Si layer 15. This layer can be the surface layer of a bulk single-crystal Si wafer. It can also be a single-crystal Si layer with or without mechanical strain which has been obtained by a first deposition of a layer of single- crystal Si_xGe_1-X having a continuously varying composition x, in the range 0.5-1 on a single- crystal Si wafer, followed by a deposition of a single-crystal layer of Si. If the separation of the single-crystal Si layer 15 is done by means of the Smart Cut method, an ion-implantation also forms part of the preparation of the handle wafer 16. The implanted ions will define the thickness of single-crystal Si layer 15 by being accumulated in a narrow region 17. Single-crystal Si layer 15 can also be part of an SOI wafer, in case of which the layer is separated from the handle wafer by an oxide layer located in region 17. The single-crystal Si layer preferably has a thickness in the range 50 - 200 nm. It can have any suitable surface orientation, including those of (100), (110) and (111).

Poly-Si layer 12 can be polished, e.g. by means of CMP, to an RMS roughness preferably not exceeding 1 nm in order to prepare the surface for the subsequent bonding. Mechanically, the presence of poly-Si layer 12 is part of the optimization in that it eliminates the need for polishing the surface of the SiC wafer 10. The latter surface is mechanically extremely hard and therefore very difficult to polish. Since polishing techniques for SiC do exist, it is however possible to polish the surface of the SiC-wafer and forgo poly-Si layer 12. Dopant atoms that were not added previously can here be added to poly-Si layer 12 by means of ion implantation.

Poly-Si layer 13, if present, is treated in manners similar to those of poly-Si layer 12.

Handle wafer 16 is oriented such that single-crystal Si layer 15, with or without a poly-Si layer 13, faces SiC wafer 10, the latter being with or without poly-Si layer 12. The two wafers are then brought into contact and will adhere spontaneously if the surfaces have been treated properly. If necessary, the wafers can be clamped together. The wafers will be more strongly bonded in a heat-treatment cycle that can either be based on RTA or furnace annealing. The heat-treatment cycle is designed in such a way that not only is bonding promoted, but also re-crystallization of the poly-Si into large-grained poly-Si, as well as activation of any dopant atoms in the poly-Si. In the case of RTA, the preferred temperatures and times to obtain this fall in the ranges 900 - 1100 °C and 10 - 30 seconds, respectively. In the case of furnace annealing, the preferred temperatures and times fall in the ranges 600 - 1100 °C and 80 - 20 minutes, respectively. In the case of the Smart Cut method, the heat-treatment cycle also involves the separation of single- crystal Si layer 15 from handle wafer 16. Another method for obtaining separation of single- crystal Si layer 15 is removal of the back part 14 of handle wafer 16 by means of CMP. Still another way is selectively etching away handle wafer 16 down to a previously introduced etch- stop layer 17. Etch-stop layer 17 can be a Si_xGe_1-x layer, where x is 0.25-1, and which is introduced prior to the deposition of single-crystal Si layer 15 on handle wafer 16. Etch-stop layer 17 can also consist of the oxide layer that forms part of an SOI handle wafer. The etch-stop layer is then removed by an additional selective-etching step.

In FIG. 2, SiC wafer 10 with its coating of a diamond-like layer 11 and single-crystal Si layer 15 is joined by an intermediate layer 21. Intermediate layer 21 consists of poly-Si and was formed from poly-Si layers 12 and 13 in FIG. 1 during the heat-treatment cycle. In FIG. 2, single-crystal

Si layer 15 can also consist of single-crystal Si_xGe_1-x, with x having a specific value in the range

0 = x = 1. Alternatively, single-crystal Si layer 15 can also consist of a single-crystal Si_xGe_1-x sublayer 15a with x having a specific value in the range 0= x = 1 on top of a single-crystal Si_xGe_1-x sublayer 15b with x having a range of values within the range 0 = x = 1. Likewise, intermediate layer 21 can consist of poly Si_xGe_1-x, with x having a specific or a range of values value in the interval 0 = x = 1. Intermediate layer 21 can also consist of one part in forms already described and denoted 21a in FIG. 2, and another part 21b, the latter being silicon oxide-based.

The complete hybrid wafer, which consists of SiC wafer 10, diamond-like coating 11, intermediate layer 21 and single-crystal layer 15 are jointly denoted by 20 in FIG. 2.

The hybrid wafer provides for an extensive degree of integration of components made from Si and SiC respectively. Thus, the single-crystal Si layer and the recrystallized poly-Si intermediate layer can be etched away to form openings to the underlying SiC. Here, SiC components can be made and also be connected to components in the single-crystal Si layer as needed. The result is an IC chip with Si and SiC components interconnected by the shortest possible signal paths, with the result that signal losses and time delays are minimized. The fact that the Si components rest on a highly heat-conducting substrate means that they will be able to handle considerably higher power-levels than in the usual case, where the Si components are located on separate IC all-Si chips. An application well suited for this type of IC chip would be that of a power supply with SiC diodes controlled by adjacent Si electronics. Another application is that of SiC based sensors integrated with Si based signal-processing and control circuits for monitoring of processes in equipment and machinery running at elevated temperatures.

The hybrid wafer provides for an integration driven even further. Thus, components made from III-V type of materials can be included on the same chip as the Si and SiC components. As an example of this, openings are etched through the single-crystal Si layer and the recrystallized poly-Si intermediate layer as was the case for the SiC components. In these openings, GaN is grown, either on top of a pre-grown Si layer, or directly on the exposed SiC surface. Components are then made in the GaN layer and connections to the other components on the IC chip are established. The result is a single IC chip with any and all combinations of Si, GaN and SiC components possible. The components are interconnected by conductor patterns forming the shortest possible signal paths. This means that signal losses and time delays will be minimized. The fact that the Si and GaN components now rest on a highly heat-conducting substrate means that they will be able to handle considerably higher power levels than in the usual case where these components are located on separate Si based IC chips. Although GaN has here been used as an example, materials such as GaN, AlGaN or AlN can be grown or deposited in the openings in combinations dictated by the requirements of the particular components to be manufacture in these openings.

It is to be understood that the hybrid wafer described above with reference to FIGs 1 and 2 may comprise more than one single-crystal Si layer 15, each layer having different surface orientation. By introducing a single-crystal Si layer with (111) surface orientation in-between the SiC wafer 10 and a single-crystal Si layer with (100) or (110) surface orientation, and making openings down to the (111) layer, III-V type materials such as nitride-based semiconductors can be grown on the (111) surface. Moreover, by making openings all the way down to the SiC surface, components made from III-V type of materials can be included on the same chip as the Si and SiC components.

The applications with substrate wafers made from Group III nitrides mentioned earlier do not exclude the use of SiC component integration in IC circuit chips. Such integration can still be obtained by building the necessary SiC components in deposited layers of SiC, analogously for the case for GaN above. It should be noted that all grown or deposited layers referred to in this description can be in the form of amorphous, polycrystalline or single-crystal layers or combinations thereof, as required by the desired properties of the components to be built in these layers. The single-crystal layers can be in the form of a hetero- or homo-epitaxial layer, or combinations of such hetero- or homo- epitaxial layers.

For a more detailed description, FIGs 3 A - 3E depict an essential aspect of the invention which involves the utilization of hybrid wafer 20 consisting of Si on SiC for the manufacture of a hybrid wafer having a hybrid-oriented surface layer of Si. FIG. 3 A shows a cross-section through SiC wafer 10, intermediate layer 21 and single-crystal Si layer 15. In FIG 3 B, hybrid wafer 20, is thermally oxidized to create a thin layer 116 on the silicon surface, said layer consisting of SiO₂ with a preferred thickness in the range 3-8 nm. Layer 116 will later on in the process serve as an etch stop. Layer 116 is made so thin that it can be dissolved during a final heat treatment at high temperature. A second silicon layer 117, with a preferred thickness in the range 50- 200 nm and having a different surface orientation than layer 15 is wafer bonded on to the oxidized silicon film in a manner analogous to that described above. If the second layer 117 is the last single- crystal Si layer to be bonded to the hybrid wafer, the layer transfer technique SmartCut can thus be used for this purpose. By way of example the single-crystal layer 15 has surface orientation (100) and single-crystal layer 117 of FIGs 3A-3E has surface orientation (110). Layer 117 is orientated such that the <110> crystal direction aligns with the <110> direction of layer 15. That will ensure that gates of n- and p-MOS transistors can have same parallel orientation. The bonding interface is subsequently strengthened by a high-temperature annealing step. The temperature is selected not high enough to dissolve the thin oxide layer 116. In FIG. 3 C, composite wafer 20+116+117 is coated with photoresist layer 118. Layer 118 is lithographically patterned to define windows 119 at the locations of the future n-MOS transistors. Layer is selectively etched away in windows 119 using dry etching with oxide layer 116 serving as an etch stop. Layer 116 is thereafter removed in windows 119 by wet etching. FIG 3D shows a cross-section of the structure after removal of remaining photo-resist layer 118. Hybrid wafer 123 now consists of two layers, Si layer 15 with the surface orientation (100) and Si layer 117 with surface orientation (110). Oxide layer 116 in FIG. 3C has been dissolved away in a high- temperature anneal as described below and is in FIG. 3D replaced by Si-Si interface 125, the latter having been simultaneously strengthened and stabilized by said high-temperature anneal. Epitaxial silicon with a preferred thickness of approximately l,5um is grown on exposed layer surfaces 15a and 117a. For physical reasons, the growth rate will be faster on the (100) surface 15a than on the (110) surface 117a. FIG 3 E shows a cross-section of the structure with the epitaxially grown layer. The latter has two different surface orientations viz. (100) in layer orientation-part 123 and (110) in layer orientation-part 124. Effects, possibly detrimental to the functioning of the LDMOS devices and caused by dislocations occurring at intersection 127 between layer orientation-part 123 and layer orientation-part 124, will not be a problem since these intersections can be electrically isolated using trench methods and also placed far from active component areas. Methods for avoiding extensive defect generation at places like intersection 127 are discussed in the abovementioned paper by Min Yang et.al. Since the epitaxial growth rate depends on the surface orientation, there will be height differences between layer orientation-parts 123 and 124. In order to compensate for this, the surface is CMP -treated after epitaxy so that a flat surface is obtained.

FIG. 3F show a cross-section of the completed hybrid wafer 128, consisting of a SiC substrate 10, an intermediate layer 21, and two mono-crystalline silicon layers with different surface orientations 15, 123 and 117, 124.

The dissolution of oxide layer 116 mentioned above can be made at a temperature in the range 1050 to 1300°C, preferably 1150 to 1250°C, for an oxide thickness in the range 0.5 to 500 nm, preferably 0.5 to 50 nm. The oxide layer will then be completely dissolved after a time in the range 10 min to a few hours, a time which is long enough to allow full control of the dissolution process. It should be noted that the invention does not exclude a similarly thin oxide layer anywhere in the bonding region between the SiC carrier and the silicon layer to be bonded to the SiC carrier. This holds regardless of whether or not poly-layers are involved in the bonding.

It should be noted here that the orders of the hybrid-oriented layers in the descriptions above are just examples and do not limit the invention. The silicon layer orientations (100), (110) and (111) can be used in any combination. It is also possible to have two layers of the same orientation in the hybrid-oriented surface layer.

Fig. 4 schematically illustrates one example of a hybrid wafer comprising three single-crystal Si layers of different surface orientation, namely a first single-crystal Si layer 15 with a (111) surface orientation next to a high thermal conductivity layer 10, a second single-crystal Si layer 117 with a (100) surface orientation, and a third single crystal Si layer 120 with a (110) surface orientation. Preferably an intermediate layer 21 is present in-between the single-crystal Si layers and the high thermal conductivity layer. As just mentioned openings have been etched through both the third and the second single-crystal Si layers in order to form openings to the underlying (111) layer. In the openings III- V semiconductor material 62, in this particular example GaN, has been grown. As illustrated, openings are also formed in the first single-crystal Si layer to the underlying (100) layer. This will enable parallel orientation of the gates of the n- and p-MOS transistors on the same wafer by utilizing the single-crystal Si layers with (100) and (110) orientations as discussed above. Thus GaN components can be formed on the same wafer as these n- and p-MOS transistors without having a single-crystal SiC substrate.

In addition to serving as a possible layer for components, or as a template surface for the growth of a nitride-based semiconductor, the (111) layer can also be made to at least partly take over the role of a poly-layer. For this, the (111) layer can be made amorphous or polycrystalline by means of ion implantation in accordance with methods well known in the field.

After this detailed description of the constituents of the invention's hybrid substrate with a hybrid-oriented Si surface layer containing differently oriented regions, the latter layer will in what follows simply be referred to as a single-crystal Si layer.

For a more detailed description, FIG. 5A depicts an essential aspect of the invention which involves the utilization of hybrid wafer 128 for the manufacture of IC components in Si as well as SiC. FIG. 5 A is a cross-section through SiC wafer 10, intermediate layer 21 and single-crystal Si layer 15. Hybrid wafer 128 has been coated with a layer of patterned photoresist 31 as part of the IC manufacturing process. A window 32 illustrates the patterned photoresist. Window 32 is used to selectively etch away the underlying part of single-crystal Si layer 15 and intermediate layer 21 as indicated by an arrow in order to reach SiC wafer 10. If SiC wafer 10 has a diamond- like coating 11, as was illustrated in FIG. 1, this coating is removed by means of plasma etching. After removal of photoresist 31, hybrid wafer 128 will have exposed Si areas adjacent to exposed areas with SiC. FIG. 5B depicts one embodiment with IC components in single-crystal Si layer 15 and in SiC wafer 10. Shown in FIG. 5B are Si components 41 built in Si layer 15 and SiC components 42 built in SiC wafer 10. The Si components 41 can be connected electrically to SiC components 42 by means of conductors 43 made from deposited and patterned metal' films. It is thus possible to obtain hybrid circuits where SiC components 42 communicate with and are electrically controlled by Si components 41 through a minimum of necessary electrical interconnects and with a highly efficient means of dissipating the heat generated in the components through the thermally highly conducting SiC wafer 10.

FIG. 6 depicts an essential part which involves the utilization of hybrid wafer 128 for an additional integration of IC components of materials from the III- V groups in the periodic table. This enables an integration of not only Si components 41 and SiC components 42, as already shown in FIG. 5, but of any combination of components based on Si, SiC and III- V. FIG. 6 illustrates one step in a process leading up to such an integration and shows how the already manufactured Si-based components 41 in single-crystal Si layer 15 and the SiC components 42 in SiC wafer 10 are covered by a protective layer 52. Protective layer 52 is preferably made from deposited silicon nitride or silicon dioxide or a mixture thereof. On top of protective layer 52, a layer 51 of photoresist is deposited and patterned. Shown in FIG. 6 is a window 53 in patterned photoresist 51. GaN or AlGaN is selectively grown in window 53, either directly on the SiC surface, or after a prior selective growth of an epitaxial Si film in window 53.

In FIG. 7, GaN-components 62 have been manufactured in the grown GaN or AlGaN layer 61. Protective layer 52 in FIG. 6 has been removed. The Si components 41, the SiC components 42 and the GaN components 62 can be connected electrically by means of conductors made from deposited and patterned metal films in patterns dictated by the circuit design. This illustrates an embodiment with IC components of several materials on one single SiC-based wafer, thus permitting an integration of not only components of different kinds, but also of different materials on one single SiC chip, thus forming a highly integrated chip. Characteristic is the possibility to minimize the electrical interconnects and the highly efficient means of removing the heat generated in the multi-material components.

Referring to Fig. 8, as described above one embodiment of a method of manufacturing a hybrid wafer comprising a hybrid-oriented surface layer on a high thermal conductivity layer 10 comprises the steps of:

- 1001 providing the high thermal conductivity layer 10; - 1002 forming an intermediate layer 21 ;

- 1003 providing a first handle wafer with a first single-crystal Si_xGe_1-x layer 15;

- 1004 transferring to the high thermal conductivity layer by bonding;

- 1006 providing a second handle wafer with a second single-crystal Si_xGei_-x layer 117, the first single-crystal Si_xGe_1-x layer 15 and the second single-crystal Si_xGei_-x layer 117 having different surface orientation; and

- 1007 transferring the second single-crystal Si_xGe_1-x layer 117 on to the first single-crystal

SiχGe_1-x layer 15.

As appreciated from the foregoing description the method is not limited to two single-crystal layers and the method can further be modified by adding sub-steps such as the step of 1009 fluorine doping the intermediate layer 21. In one embodiment of the present invention the method further comprises the steps of 1005 oxidizing the first single-crystal Si_xGe_1-x layer 15 in order to form an oxide layer 116 before transferring of the second single-crystal Si_xGe_1-x layer 117 and 1008 heat treating the hybrid wafer in order to dissolve the oxide layer 116.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, on the contrary, it is intended to cover various modifications and equivalent arrangements within the appended claims.

Claims

1. A hybrid wafer characterized in that the hybrid wafer comprises a hybrid-oriented surface layer on a high thermal conductivity layer (10), the hybrid-oriented surface layer comprises a first single-crystal Si_xGe_1-x layer (15), where 0 < x < 1, and a second single-crystal Si_xGe]- _x layer (117), where 0 < x <1, and the first and the second single-crystal Si_xGe_1-x layers (15,117) have different surface orientation.

2. The hybrid wafer according to claim 1, further comprising between the first single-crystal Si_xGei_-x layer (15) and the high thermal conductivity layer (10), an intermediate layer (21) comprising at least one amorphous or polycrystalline Si_xGe_{1 -x} layer (21a), where 0 < x <1.

3. The hybrid wafer according to claim 1 or 2, wherein the hybrid-oriented surface layer further comprises a third single- crystal Si_xGe _1-x layer, where 0 < x < 1, the surface orientation of the third single-crystal Si_xGe_1-x layer (120) being different from the surface orientation of the first and the second single-crystal Si_xGe_1-x layers (15,117).

4. The hybrid wafer according to anyone of claims 1 to 3, wherein the single-crystal Si_xGe_1-x layers (15,117, 120) includes two or more of the surface orientations (100), (110) and (111).

5. The hybrid wafer according to claim 2 or 3, wherein the intermediate layer (21) is doped with fluorine.

6. The hybrid wafer according to anyone of claims 1 to 5 wherein the at least one of said Si_xGei_-x layers (15,117, 120) comprises at least one pre-manufactured IC component.

7. The hybrid wafer according to anyone of claims 2 to 6, wherein the intermediate layer (21) is doped to a specific electric conductivity such that it forms an electrically conductive layer.

8. The hybrid wafer according to anyone of claims 1 to 7, wherein the high thermal conductivity layer (10) comprises a mono-crystalline material.

9. The hybrid wafer according to anyone of claims 1 to 7, wherein the high thermal conductivity layer (10) comprises a polycrystalline material.

10. The hybrid wafer according to claim 8 or 9, wherein the mono-crystalline or polycrystalline material is semi-insulating or doped to a specific electrical conductivity.

11. The hybrid wafer according to anyone of claims 2 to 10, wherein a diamond-like layer (11) is provided between the intermediate layer (21) and the high thermal conductivity layer (10).

12. The hybrid wafer according to anyone of claims 1 to 11, wherein the high thermal conductivity layer is made of a material selected from the group of AlN, diamond, and SiC.

13. The hybrid wafer according to anyone of claims 1 to 12, wherein the hybrid wafer comprises at least one SiC component (42) in at least one opening in the single-crystal Si_xGe_1-X layers (15,117,120), and at least one Si_xGe_1-x component (41) in at least one of the single-crystal Si_xGe_1-x layers (15,117,120), said at least one SiC component (42) and said at r least one Si_xGe_1-x component (41) together being part of at least one hybrid IC structure.

14. The hybrid wafer according to anyone of claims 1 to 13, wherein the hybrid wafer comprises at least one III-V semiconductor component (62) in at least one opening in the single-crystal Si_xGe_1-x layers (15,117,120), and at least one Si_xGe_1-x component (41) in at least one of the Si_xGe_1-x layers (15,117,120), said at least one III-V semiconductor component (62) and said at least one Si_xGe_1-x component (41) together being part of at least one hybrid IC structure.

15. The hybrid wafer according to anyone of claims 1 to 14, wherein said at least one III-V semiconductor component (62) is formed on a single-crystal Si_xGe_1-x layer (15,117,120) with surface orientation (111).

16. The hybrid layer according to anyone of claims 1 to 15, wherein the hybrid wafer comprises an oxide layer (116) between said Si_xGei_-x layers (15,117,120).

17. A method of manufacturing a hybrid wafer comprising a hybrid-oriented surface layer on a high thermal conductivity layer (10), characterized in that the method comprises the steps of:

- (1001) providing the high thermal conductivity layer (10);

- (1002) forming an intermediate layer (21);

- (1003) providing a first handle wafer with a first single-crystal Si_xGe_1-x layer (15) - (1004) transferring the first single-crystal Si_xGei_-x layer (15) to the high thermal conductivity layer by bonding;

- (1006) providing a second handle wafer with a second single-crystal Si_xGe_1-x layer (117); and

- (1007) transferring the second single-crystal Si_xGe_1-x layer (117) on to the first single- crystal Si_xGe _1-x layer (15).

18. The method of manufacturing a hybrid wafer according to claim 17, further comprising the step of (1005) oxidizing the first single-crystal Si_xGe_{1 -x} layer (15) in order to form an oxide layer (116) before transferring the second single-crystal Si_xGe_1-x layer (117).

19. The method of manufacturing a hybrid wafer according to claim 18, further comprising the step of (1008) heat treating the hybrid wafer after transferring the second single-crystal

Si_xGe_1-x layer (117) in order to dissolve the oxide layer (116).

20. The method of manufacturing a hybrid wafer according to anyone of claims 17 to 19, further comprising the step of (1009) fluorine doping the intermediate layer (21).