JP2006121036A - フラッシュメモリ素子のソースコンタクト形成方法 - Google Patents
フラッシュメモリ素子のソースコンタクト形成方法 Download PDFInfo
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- JP2006121036A JP2006121036A JP2005145071A JP2005145071A JP2006121036A JP 2006121036 A JP2006121036 A JP 2006121036A JP 2005145071 A JP2005145071 A JP 2005145071A JP 2005145071 A JP2005145071 A JP 2005145071A JP 2006121036 A JP2006121036 A JP 2006121036A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】 本発明のフラッシュメモリ素子のソースコンタクト形成方法は、セル領域のSSL用ゲート電極パターンに備えられた接合領域が形成された半導体基板の全面に層間絶縁膜を形成し、前記層間絶縁膜をパターニングし、前記SSL用ゲート電極パターンの一側で前記接合領域を露出させるソースコンタクトホールを形成する段階と、前記ソースコンタクトホールの形成された結果物の全面にタングステンシリサイド膜の含まれた膜を形成し、前記層間絶縁膜が露出するまで平坦化工程を行い、前記ソースコンタクトホール内にのみ前記タングステンシリサイド膜の含まれた膜が埋め立てられてソースコンタクトを形成する段階とを含む。
【選択図】 図2
Description
DSL DSL用ゲート電極パターン
CT セルトランジスタ
PT 周辺回路用ゲート電極パターン
24 接合領域
32 ソースコンタクト
Claims (5)
- セル領域のSSL用ゲート電極パターンに備えられた接合領域が形成された半導体基板の全面に層間絶縁膜を形成し、前記層間絶縁膜をパターニングして、前記SSL用ゲート電極パターンの一側で前記接合領域を露出させるソースコンタクトホールを形成する段階と、
前記ソースコンタクトホールの形成された結果物の全面にタングステンシリサイド膜の含まれた膜を形成し、前記層間絶縁膜が露出するまで平坦化工程を行って前記ソースコンタクトホール内にのみ前記タングステンシリサイド膜の含まれた膜が埋め立てられてソースコンタクトを形成する段階とを含むことを特徴とするフラッシュメモリ素子のソースコンタクト形成方法。 - 前記タングステンシリサイド膜の含まれた膜は、タングステンシリサイド膜、タングステンシリサイド膜/ポリシリコン膜、ポリシリコン膜/タングステンシリサイド膜、およびタングステンシリサイド膜の二重膜のいずれか一つで形成することを特徴とする請求項1記載のフラッシュメモリ素子のソースコンタクト形成方法。
- 前記タングステンシリサイド膜は、MS(SiH4)またはDSC(SiH2Cl2)−basedWSix膜を用いてCVD法によって温度330℃以上且つ450℃以下または550℃以上且つ600℃以下、圧力0.4Torr以上且つ3Torr以下の工程条件で形成することを特徴とする請求項1または2記載のフラッシュメモリ素子のソースコンタクト形成方法。
- 前記ソースコンタクトの形成された結果物の全面に層間絶縁膜を形成し、前記層間絶縁膜をパターニングして、周辺回路領域の周辺回路用ゲート電極パターンに形成された前記接合領域を露出させる段階と、
前記周辺回路領域の周辺回路用ゲート電極パターンに形成された前記接合領域が露出した結果物の全面にイオン注入工程を行い、熱処理工程を行って前記接合領域に熱処理済みの接合領域を形成する段階とをさらに含むことを特徴とする請求項1記載のフラッシュメモリ素子のソースコンタクト形成方法。 - 前記熱処理工程は、850℃以上且つ1000℃以下の温度範囲で約20分間以上且つ40分間以下行われる工程条件、または900℃以上且つ1000℃以下の温度範囲で約10秒間以上且つ20秒間以下行われる条件とすることを特徴とする請求項4記載のフラッシュメモリ素子のソースコンタクト形成方法。
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KR1020040085428A KR100671627B1 (ko) | 2004-10-25 | 2004-10-25 | 플래쉬 메모리소자의 소스 콘택 형성방법 |
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JP2006121036A true JP2006121036A (ja) | 2006-05-11 |
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JP2005145071A Pending JP2006121036A (ja) | 2004-10-25 | 2005-05-18 | フラッシュメモリ素子のソースコンタクト形成方法 |
Country Status (4)
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US (1) | US7268041B2 (ja) |
JP (1) | JP2006121036A (ja) |
KR (1) | KR100671627B1 (ja) |
DE (1) | DE102005022372B4 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007318065A (ja) * | 2006-05-26 | 2007-12-06 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
JP2008091909A (ja) * | 2006-09-28 | 2008-04-17 | Hynix Semiconductor Inc | 半導体素子のコンタクトプラグ形成方法 |
KR100875054B1 (ko) | 2006-12-28 | 2008-12-19 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성 방법 |
Families Citing this family (10)
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JP4578938B2 (ja) * | 2004-11-08 | 2010-11-10 | 富士通セミコンダクター株式会社 | 半導体装置 |
KR100680465B1 (ko) * | 2005-06-30 | 2007-02-08 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
JP4364225B2 (ja) * | 2006-09-15 | 2009-11-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR100761409B1 (ko) * | 2006-09-29 | 2007-09-27 | 주식회사 하이닉스반도체 | 플래시 메모리 소자 및 그 제조방법 |
KR100831158B1 (ko) * | 2006-12-20 | 2008-05-20 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자의 제조방법 |
US8114736B2 (en) * | 2006-12-21 | 2012-02-14 | Globalfoundries Inc. | Integrated circuit system with memory system |
KR100830591B1 (ko) * | 2007-06-07 | 2008-05-22 | 삼성전자주식회사 | 개구부들을 포함하는 반도체 소자의 형성 방법 |
KR101010467B1 (ko) * | 2007-09-10 | 2011-01-21 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성방법 |
KR100884979B1 (ko) | 2007-11-22 | 2009-02-23 | 주식회사 동부하이텍 | 플래시 메모리 소자의 제조방법 |
KR20090068730A (ko) * | 2007-12-24 | 2009-06-29 | 주식회사 동부하이텍 | 반도체 소자 및 그의 제조 방법 |
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2004
- 2004-10-25 KR KR1020040085428A patent/KR100671627B1/ko not_active IP Right Cessation
-
2005
- 2005-05-10 DE DE102005022372A patent/DE102005022372B4/de not_active Expired - Fee Related
- 2005-05-18 JP JP2005145071A patent/JP2006121036A/ja active Pending
- 2005-05-27 US US11/138,694 patent/US7268041B2/en active Active
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JP2007318065A (ja) * | 2006-05-26 | 2007-12-06 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
JP2008091909A (ja) * | 2006-09-28 | 2008-04-17 | Hynix Semiconductor Inc | 半導体素子のコンタクトプラグ形成方法 |
KR100875054B1 (ko) | 2006-12-28 | 2008-12-19 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성 방법 |
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Also Published As
Publication number | Publication date |
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KR20060036545A (ko) | 2006-05-02 |
US20060110874A1 (en) | 2006-05-25 |
DE102005022372A1 (de) | 2006-04-27 |
DE102005022372B4 (de) | 2010-07-08 |
US7268041B2 (en) | 2007-09-11 |
KR100671627B1 (ko) | 2007-01-19 |
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