JP2005092969A - 不揮発性半導体記憶装置 - Google Patents

不揮発性半導体記憶装置 Download PDF

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Publication number
JP2005092969A
JP2005092969A JP2003323633A JP2003323633A JP2005092969A JP 2005092969 A JP2005092969 A JP 2005092969A JP 2003323633 A JP2003323633 A JP 2003323633A JP 2003323633 A JP2003323633 A JP 2003323633A JP 2005092969 A JP2005092969 A JP 2005092969A
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JP
Japan
Prior art keywords
circuit
signal
block
gate
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003323633A
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English (en)
Japanese (ja)
Other versions
JP2005092969A5 (https=
Inventor
Taku Ogura
卓 小倉
Tadaaki Yamauchi
忠昭 山内
Hidenori Mitani
秀徳 三谷
Takashi Kubo
貴志 久保
Kengo Aritomi
謙悟 有冨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2003323633A priority Critical patent/JP2005092969A/ja
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to KR1020040073840A priority patent/KR100629291B1/ko
Priority to US10/940,764 priority patent/US7248513B2/en
Publication of JP2005092969A publication Critical patent/JP2005092969A/ja
Priority to KR1020060026580A priority patent/KR100668540B1/ko
Publication of JP2005092969A5 publication Critical patent/JP2005092969A5/ja
Priority to US11/819,203 priority patent/US7447087B2/en
Priority to US12/251,894 priority patent/US7782672B2/en
Priority to US12/849,254 priority patent/US8000159B2/en
Priority to US13/178,182 priority patent/US8208303B2/en
Priority to US13/481,540 priority patent/US8446765B2/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B11/00—Cleaning flexible or delicate articles by methods or apparatus specially adapted thereto
    • B08B11/04—Cleaning flexible or delicate articles by methods or apparatus specially adapted thereto specially adapted for plate glass, e.g. prior to manufacture of windshields
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
    • C03C23/0085—Drying; Dehydroxylation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2003323633A 2003-09-16 2003-09-16 不揮発性半導体記憶装置 Pending JP2005092969A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2003323633A JP2005092969A (ja) 2003-09-16 2003-09-16 不揮発性半導体記憶装置
KR1020040073840A KR100629291B1 (ko) 2003-09-16 2004-09-15 반도체 기억 장치
US10/940,764 US7248513B2 (en) 2003-09-16 2004-09-15 Semiconductor memory device having memory block configuration
KR1020060026580A KR100668540B1 (ko) 2003-09-16 2006-03-23 메모리 블록 구성을 갖는 반도체 기억 장치
US11/819,203 US7447087B2 (en) 2003-09-16 2007-06-26 Semiconductor memory device having memory block configuration
US12/251,894 US7782672B2 (en) 2003-09-16 2008-10-15 Semiconductor memory device having memory block configuration
US12/849,254 US8000159B2 (en) 2003-09-16 2010-08-03 Semiconductor memory device having memory block configuration
US13/178,182 US8208303B2 (en) 2003-09-16 2011-07-07 Semiconductor memory device having memory block configuration
US13/481,540 US8446765B2 (en) 2003-09-16 2012-05-25 Semiconductor memory device having memory block configuration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003323633A JP2005092969A (ja) 2003-09-16 2003-09-16 不揮発性半導体記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010226419A Division JP5094941B2 (ja) 2010-10-06 2010-10-06 不揮発性半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2005092969A true JP2005092969A (ja) 2005-04-07
JP2005092969A5 JP2005092969A5 (https=) 2006-09-21

Family

ID=34270036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003323633A Pending JP2005092969A (ja) 2003-09-16 2003-09-16 不揮発性半導体記憶装置

Country Status (3)

Country Link
US (6) US7248513B2 (https=)
JP (1) JP2005092969A (https=)
KR (2) KR100629291B1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242735A (ja) * 2006-03-06 2007-09-20 Toshiba Corp 不揮発性半導体記憶装置

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JP2007200512A (ja) * 2006-01-30 2007-08-09 Renesas Technology Corp 半導体記憶装置
TWI370515B (en) 2006-09-29 2012-08-11 Megica Corp Circuit component
KR100871083B1 (ko) * 2007-02-27 2008-11-28 삼성전자주식회사 입출력 센스앰프를 구비하는 반도체 메모리 장치의레이아웃 구조
US9159452B2 (en) 2008-11-14 2015-10-13 Micron Technology, Inc. Automatic word line leakage measurement circuitry
US8588007B2 (en) * 2011-02-28 2013-11-19 Micron Technology, Inc. Leakage measurement systems
US8634264B2 (en) 2011-10-26 2014-01-21 Micron Technology, Inc. Apparatuses, integrated circuits, and methods for measuring leakage current
US11024352B2 (en) 2012-04-10 2021-06-01 Samsung Electronics Co., Ltd. Memory system for access concentration decrease management and access concentration decrease method
US10097086B2 (en) * 2016-10-12 2018-10-09 Cypress Semiconductor Corporation Fast ramp low supply charge pump circuits
TW202301125A (zh) * 2017-07-30 2023-01-01 埃拉德 希提 具有以記憶體為基礎的分散式處理器架構的記憶體晶片
CN118692545A (zh) * 2021-03-24 2024-09-24 长江存储科技有限责任公司 使用冗余存储体进行故障主存储体修复的存储器件

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JPH08125143A (ja) * 1994-10-27 1996-05-17 Nec Corp 半導体記憶装置
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Publication number Priority date Publication date Assignee Title
JP2007242735A (ja) * 2006-03-06 2007-09-20 Toshiba Corp 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US20110261617A1 (en) 2011-10-27
KR100629291B1 (ko) 2006-09-28
US8208303B2 (en) 2012-06-26
US20120230107A1 (en) 2012-09-13
US7447087B2 (en) 2008-11-04
US7248513B2 (en) 2007-07-24
US20110002170A1 (en) 2011-01-06
US20070297251A1 (en) 2007-12-27
KR20060040616A (ko) 2006-05-10
US20050057963A1 (en) 2005-03-17
US8000159B2 (en) 2011-08-16
KR100668540B1 (ko) 2007-01-16
US20090052249A1 (en) 2009-02-26
US7782672B2 (en) 2010-08-24
US8446765B2 (en) 2013-05-21
KR20050027956A (ko) 2005-03-21

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