KR100629291B1 - 반도체 기억 장치 - Google Patents
반도체 기억 장치 Download PDFInfo
- Publication number
- KR100629291B1 KR100629291B1 KR1020040073840A KR20040073840A KR100629291B1 KR 100629291 B1 KR100629291 B1 KR 100629291B1 KR 1020040073840 A KR1020040073840 A KR 1020040073840A KR 20040073840 A KR20040073840 A KR 20040073840A KR 100629291 B1 KR100629291 B1 KR 100629291B1
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- circuit
- block
- level
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B08—CLEANING
- B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
- B08B11/00—Cleaning flexible or delicate articles by methods or apparatus specially adapted thereto
- B08B11/04—Cleaning flexible or delicate articles by methods or apparatus specially adapted thereto specially adapted for plate glass, e.g. prior to manufacture of windshields
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
- C03C23/0085—Drying; Dehydroxylation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
- G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geochemistry & Mineralogy (AREA)
- Materials Engineering (AREA)
- Organic Chemistry (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2003-00323633 | 2003-09-16 | ||
| JP2003323633A JP2005092969A (ja) | 2003-09-16 | 2003-09-16 | 不揮発性半導体記憶装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020060026580A Division KR100668540B1 (ko) | 2003-09-16 | 2006-03-23 | 메모리 블록 구성을 갖는 반도체 기억 장치 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050027956A KR20050027956A (ko) | 2005-03-21 |
| KR100629291B1 true KR100629291B1 (ko) | 2006-09-28 |
Family
ID=34270036
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020040073840A Expired - Fee Related KR100629291B1 (ko) | 2003-09-16 | 2004-09-15 | 반도체 기억 장치 |
| KR1020060026580A Expired - Fee Related KR100668540B1 (ko) | 2003-09-16 | 2006-03-23 | 메모리 블록 구성을 갖는 반도체 기억 장치 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020060026580A Expired - Fee Related KR100668540B1 (ko) | 2003-09-16 | 2006-03-23 | 메모리 블록 구성을 갖는 반도체 기억 장치 |
Country Status (3)
| Country | Link |
|---|---|
| US (6) | US7248513B2 (https=) |
| JP (1) | JP2005092969A (https=) |
| KR (2) | KR100629291B1 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007200512A (ja) * | 2006-01-30 | 2007-08-09 | Renesas Technology Corp | 半導体記憶装置 |
| JP4843336B2 (ja) * | 2006-03-06 | 2011-12-21 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| TWI370515B (en) | 2006-09-29 | 2012-08-11 | Megica Corp | Circuit component |
| KR100871083B1 (ko) * | 2007-02-27 | 2008-11-28 | 삼성전자주식회사 | 입출력 센스앰프를 구비하는 반도체 메모리 장치의레이아웃 구조 |
| US9159452B2 (en) | 2008-11-14 | 2015-10-13 | Micron Technology, Inc. | Automatic word line leakage measurement circuitry |
| US8588007B2 (en) * | 2011-02-28 | 2013-11-19 | Micron Technology, Inc. | Leakage measurement systems |
| US8634264B2 (en) | 2011-10-26 | 2014-01-21 | Micron Technology, Inc. | Apparatuses, integrated circuits, and methods for measuring leakage current |
| US11024352B2 (en) | 2012-04-10 | 2021-06-01 | Samsung Electronics Co., Ltd. | Memory system for access concentration decrease management and access concentration decrease method |
| US10097086B2 (en) * | 2016-10-12 | 2018-10-09 | Cypress Semiconductor Corporation | Fast ramp low supply charge pump circuits |
| TW202301125A (zh) * | 2017-07-30 | 2023-01-01 | 埃拉德 希提 | 具有以記憶體為基礎的分散式處理器架構的記憶體晶片 |
| CN118692545A (zh) * | 2021-03-24 | 2024-09-24 | 长江存储科技有限责任公司 | 使用冗余存储体进行故障主存储体修复的存储器件 |
Family Cites Families (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6230233B1 (en) * | 1991-09-13 | 2001-05-08 | Sandisk Corporation | Wear leveling techniques for flash EEPROM systems |
| JPH06119230A (ja) * | 1992-10-06 | 1994-04-28 | Fujitsu Ltd | 半導体記憶装置 |
| KR0137105B1 (ko) * | 1993-06-17 | 1998-04-29 | 모리시다 요이치 | 데이터 전송회로, 데이터선 구동회로, 증폭회로, 반도체 집적회로 및 반도체 기억장치 |
| JPH0729386A (ja) * | 1993-07-13 | 1995-01-31 | Hitachi Ltd | フラッシュメモリ及びマイクロコンピュータ |
| JP3301047B2 (ja) * | 1993-09-16 | 2002-07-15 | 株式会社日立製作所 | 半導体メモリシステム |
| JP2647023B2 (ja) * | 1994-10-27 | 1997-08-27 | 日本電気株式会社 | 半導体記憶装置 |
| US6075743A (en) * | 1996-12-26 | 2000-06-13 | Rambus Inc. | Method and apparatus for sharing sense amplifiers between memory banks |
| JP3964491B2 (ja) * | 1997-03-25 | 2007-08-22 | 株式会社ルネサステクノロジ | 半導体記憶装置及び半導体記憶装置の欠陥救済方法 |
| JP3497708B2 (ja) * | 1997-10-09 | 2004-02-16 | 株式会社東芝 | 半導体集積回路 |
| US6002620A (en) * | 1998-01-09 | 1999-12-14 | Information Storage Devices, Inc. | Method and apparatus of column redundancy for non-volatile analog and multilevel memory |
| JPH11203862A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6154819A (en) * | 1998-05-11 | 2000-11-28 | Intel Corporation | Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks |
| JP2000067595A (ja) * | 1998-06-09 | 2000-03-03 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP4179687B2 (ja) * | 1998-12-24 | 2008-11-12 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US6975539B2 (en) * | 1999-01-14 | 2005-12-13 | Silicon Storage Technology, Inc. | Digital multilevel non-volatile memory system |
| JP2000228501A (ja) * | 1999-02-08 | 2000-08-15 | Sanyo Electric Co Ltd | 半導体メモリ装置 |
| JP2001143494A (ja) * | 1999-03-19 | 2001-05-25 | Toshiba Corp | 半導体記憶装置 |
| JP2001052495A (ja) * | 1999-06-03 | 2001-02-23 | Toshiba Corp | 半導体メモリ |
| JP2001014890A (ja) * | 1999-06-30 | 2001-01-19 | Mitsubishi Electric Corp | 半導体装置および半導体装置のテスト方法 |
| JP3844917B2 (ja) * | 1999-07-26 | 2006-11-15 | 株式会社東芝 | 半導体記憶装置 |
| JP3859912B2 (ja) | 1999-09-08 | 2006-12-20 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP3937214B2 (ja) * | 1999-09-17 | 2007-06-27 | 株式会社ルネサステクノロジ | エラー訂正回数を記録する記憶装置 |
| JP2001266589A (ja) * | 2000-03-21 | 2001-09-28 | Toshiba Corp | 半導体記憶装置およびそのテスト方法 |
| JP4398574B2 (ja) * | 2000-07-19 | 2010-01-13 | 富士通マイクロエレクトロニクス株式会社 | 半導体記憶装置とその冗長方法 |
| JP2002109899A (ja) * | 2000-07-26 | 2002-04-12 | Mitsubishi Electric Corp | 半導体記憶装置およびそれを備える半導体集積回路装置 |
| US6483044B1 (en) * | 2000-08-23 | 2002-11-19 | Micron Technology, Inc. | Interconnecting substrates for electrical coupling of microelectronic components |
| JP3916862B2 (ja) | 2000-10-03 | 2007-05-23 | 株式会社東芝 | 不揮発性半導体メモリ装置 |
| JP3680725B2 (ja) * | 2000-10-26 | 2005-08-10 | 松下電器産業株式会社 | 半導体記憶装置 |
| JP2002150789A (ja) * | 2000-11-09 | 2002-05-24 | Hitachi Ltd | 不揮発性半導体記憶装置 |
| US6563743B2 (en) * | 2000-11-27 | 2003-05-13 | Hitachi, Ltd. | Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy |
| JP4049297B2 (ja) * | 2001-06-11 | 2008-02-20 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP2003077293A (ja) * | 2001-08-31 | 2003-03-14 | Toshiba Corp | 半導体装置 |
| JP4033438B2 (ja) * | 2001-09-04 | 2008-01-16 | 株式会社東芝 | 半導体記憶装置 |
| FR2831315B1 (fr) * | 2001-10-22 | 2004-01-30 | St Microelectronics Sa | Memoire eeprom comprenant des moyens de lecture simultanee de bits speciaux d'un premier et d'un second type |
| JP4322686B2 (ja) * | 2004-01-07 | 2009-09-02 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US7068555B2 (en) * | 2004-02-20 | 2006-06-27 | Spansion Llc | Semiconductor memory storage device and a redundancy control method therefor |
| FR2888660B1 (fr) * | 2005-07-13 | 2007-10-05 | St Microelectronics Sa | Systeme redondance colonne pour une memoire en circuit integre |
| JP5002967B2 (ja) * | 2006-01-24 | 2012-08-15 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| KR101471574B1 (ko) * | 2008-04-10 | 2014-12-24 | 삼성전자주식회사 | 반도체 칩과 반도체 장치 |
-
2003
- 2003-09-16 JP JP2003323633A patent/JP2005092969A/ja active Pending
-
2004
- 2004-09-15 US US10/940,764 patent/US7248513B2/en not_active Expired - Fee Related
- 2004-09-15 KR KR1020040073840A patent/KR100629291B1/ko not_active Expired - Fee Related
-
2006
- 2006-03-23 KR KR1020060026580A patent/KR100668540B1/ko not_active Expired - Fee Related
-
2007
- 2007-06-26 US US11/819,203 patent/US7447087B2/en not_active Expired - Fee Related
-
2008
- 2008-10-15 US US12/251,894 patent/US7782672B2/en not_active Expired - Lifetime
-
2010
- 2010-08-03 US US12/849,254 patent/US8000159B2/en not_active Expired - Fee Related
-
2011
- 2011-07-07 US US13/178,182 patent/US8208303B2/en not_active Expired - Fee Related
-
2012
- 2012-05-25 US US13/481,540 patent/US8446765B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20110261617A1 (en) | 2011-10-27 |
| JP2005092969A (ja) | 2005-04-07 |
| US8208303B2 (en) | 2012-06-26 |
| US20120230107A1 (en) | 2012-09-13 |
| US7447087B2 (en) | 2008-11-04 |
| US7248513B2 (en) | 2007-07-24 |
| US20110002170A1 (en) | 2011-01-06 |
| US20070297251A1 (en) | 2007-12-27 |
| KR20060040616A (ko) | 2006-05-10 |
| US20050057963A1 (en) | 2005-03-17 |
| US8000159B2 (en) | 2011-08-16 |
| KR100668540B1 (ko) | 2007-01-16 |
| US20090052249A1 (en) | 2009-02-26 |
| US7782672B2 (en) | 2010-08-24 |
| US8446765B2 (en) | 2013-05-21 |
| KR20050027956A (ko) | 2005-03-21 |
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| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
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| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
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| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
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| A107 | Divisional application of patent | ||
| E13-X000 | Pre-grant limitation requested |
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