CN109427374A - 半导体存储装置 - Google Patents
半导体存储装置 Download PDFInfo
- Publication number
- CN109427374A CN109427374A CN201810149119.3A CN201810149119A CN109427374A CN 109427374 A CN109427374 A CN 109427374A CN 201810149119 A CN201810149119 A CN 201810149119A CN 109427374 A CN109427374 A CN 109427374A
- Authority
- CN
- China
- Prior art keywords
- selection
- wordline
- sel
- power circuit
- bit lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017-164763 | 2017-08-29 | ||
JP2017164763A JP2019046514A (ja) | 2017-08-29 | 2017-08-29 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109427374A true CN109427374A (zh) | 2019-03-05 |
CN109427374B CN109427374B (zh) | 2022-11-04 |
Family
ID=65434294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810149119.3A Active CN109427374B (zh) | 2017-08-29 | 2018-02-13 | 半导体存储装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10418074B2 (zh) |
JP (1) | JP2019046514A (zh) |
CN (1) | CN109427374B (zh) |
TW (1) | TWI655639B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111883190A (zh) * | 2019-05-03 | 2020-11-03 | 爱思开海力士有限公司 | 电子器件以及电子器件的操作方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020000873A1 (en) * | 1999-01-04 | 2002-01-03 | Hiroaki Tanizaki | Semiconductor device having hierarchical power supply line structure improved in operating speed |
CN1432920A (zh) * | 2002-01-15 | 2003-07-30 | 三星电子株式会社 | Nand闪存装置 |
US20060083078A1 (en) * | 2004-10-15 | 2006-04-20 | Stmicroelectronics S.R.I. | Memory device |
US20070195946A1 (en) * | 2006-02-17 | 2007-08-23 | Fujitsu Limited | Semiconductor integrated circuit device |
CN101866686A (zh) * | 2004-09-15 | 2010-10-20 | 瑞萨电子株式会社 | 半导体集成电路器件 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06104608A (ja) * | 1992-09-24 | 1994-04-15 | Matsushita Electric Ind Co Ltd | フィルタ |
US7177181B1 (en) | 2001-03-21 | 2007-02-13 | Sandisk 3D Llc | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics |
US6778431B2 (en) | 2002-12-13 | 2004-08-17 | International Business Machines Corporation | Architecture for high-speed magnetic memories |
US7050345B1 (en) * | 2004-07-29 | 2006-05-23 | Sheppard Douglas P | Memory device and method with improved power and noise characteristics |
TWI460918B (zh) * | 2010-07-30 | 2014-11-11 | Univ Nat Taiwan | 共模雜訊抑制電路 |
JP6107472B2 (ja) | 2012-06-28 | 2017-04-05 | 凸版印刷株式会社 | 不揮発性メモリセル、およびこの不揮発性メモリセルを備えた不揮発性メモリ |
KR101998673B1 (ko) * | 2012-10-12 | 2019-07-11 | 삼성전자주식회사 | 저항성 메모리 장치 및 그것의 구동방법 |
JP5883494B1 (ja) | 2014-11-19 | 2016-03-15 | ウィンボンド エレクトロニクス コーポレーション | 不揮発性半導体記憶装置 |
-
2017
- 2017-08-29 JP JP2017164763A patent/JP2019046514A/ja active Pending
-
2018
- 2018-01-22 TW TW107102164A patent/TWI655639B/zh active
- 2018-02-13 CN CN201810149119.3A patent/CN109427374B/zh active Active
- 2018-02-27 US US15/906,592 patent/US10418074B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020000873A1 (en) * | 1999-01-04 | 2002-01-03 | Hiroaki Tanizaki | Semiconductor device having hierarchical power supply line structure improved in operating speed |
CN1432920A (zh) * | 2002-01-15 | 2003-07-30 | 三星电子株式会社 | Nand闪存装置 |
CN101866686A (zh) * | 2004-09-15 | 2010-10-20 | 瑞萨电子株式会社 | 半导体集成电路器件 |
US20060083078A1 (en) * | 2004-10-15 | 2006-04-20 | Stmicroelectronics S.R.I. | Memory device |
US20070195946A1 (en) * | 2006-02-17 | 2007-08-23 | Fujitsu Limited | Semiconductor integrated circuit device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111883190A (zh) * | 2019-05-03 | 2020-11-03 | 爱思开海力士有限公司 | 电子器件以及电子器件的操作方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2019046514A (ja) | 2019-03-22 |
US10418074B2 (en) | 2019-09-17 |
TW201913658A (zh) | 2019-04-01 |
US20190066737A1 (en) | 2019-02-28 |
TWI655639B (zh) | 2019-04-01 |
CN109427374B (zh) | 2022-11-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: Tokyo Applicant after: Kaixia Co.,Ltd. Address before: Tokyo Applicant before: TOSHIBA MEMORY Corp. Address after: Tokyo Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo Applicant before: Pangea Co.,Ltd. |
|
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20220129 Address after: Tokyo Applicant after: Pangea Co.,Ltd. Address before: Tokyo Applicant before: TOSHIBA MEMORY Corp. |
|
GR01 | Patent grant | ||
GR01 | Patent grant |