JP2003031693A - 半導体メモリ装置 - Google Patents

半導体メモリ装置

Info

Publication number
JP2003031693A
JP2003031693A JP2001220461A JP2001220461A JP2003031693A JP 2003031693 A JP2003031693 A JP 2003031693A JP 2001220461 A JP2001220461 A JP 2001220461A JP 2001220461 A JP2001220461 A JP 2001220461A JP 2003031693 A JP2003031693 A JP 2003031693A
Authority
JP
Japan
Prior art keywords
channel body
gate
state
misfet
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001220461A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003031693A5 (https=
Inventor
Takashi Osawa
隆 大澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001220461A priority Critical patent/JP2003031693A/ja
Priority to US09/964,851 priority patent/US6617651B2/en
Priority to EP01123208A priority patent/EP1280205A3/en
Priority to TW090126711A priority patent/TW519751B/zh
Priority to KR10-2001-0069942A priority patent/KR100440188B1/ko
Priority to CN011435461A priority patent/CN1217415C/zh
Publication of JP2003031693A publication Critical patent/JP2003031693A/ja
Priority to US10/617,737 priority patent/US6897531B2/en
Publication of JP2003031693A5 publication Critical patent/JP2003031693A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
JP2001220461A 2001-07-19 2001-07-19 半導体メモリ装置 Pending JP2003031693A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2001220461A JP2003031693A (ja) 2001-07-19 2001-07-19 半導体メモリ装置
US09/964,851 US6617651B2 (en) 2001-07-19 2001-09-28 Semiconductor memory device
EP01123208A EP1280205A3 (en) 2001-07-19 2001-10-01 Semiconductor memory device
TW090126711A TW519751B (en) 2001-07-19 2001-10-29 Semiconductor memory device
KR10-2001-0069942A KR100440188B1 (ko) 2001-07-19 2001-11-10 반도체 메모리 장치
CN011435461A CN1217415C (zh) 2001-07-19 2001-12-11 半导体存储器件
US10/617,737 US6897531B2 (en) 2001-07-19 2003-07-14 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001220461A JP2003031693A (ja) 2001-07-19 2001-07-19 半導体メモリ装置

Publications (2)

Publication Number Publication Date
JP2003031693A true JP2003031693A (ja) 2003-01-31
JP2003031693A5 JP2003031693A5 (https=) 2005-07-21

Family

ID=19054277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001220461A Pending JP2003031693A (ja) 2001-07-19 2001-07-19 半導体メモリ装置

Country Status (6)

Country Link
US (2) US6617651B2 (https=)
EP (1) EP1280205A3 (https=)
JP (1) JP2003031693A (https=)
KR (1) KR100440188B1 (https=)
CN (1) CN1217415C (https=)
TW (1) TW519751B (https=)

Cited By (78)

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JP2004297048A (ja) * 2003-03-11 2004-10-21 Semiconductor Energy Lab Co Ltd 集積回路、該集積回路を有する半導体表示装置及び集積回路の駆動方法
US6825524B1 (en) 2003-08-29 2004-11-30 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
JP2005026353A (ja) * 2003-06-30 2005-01-27 Toshiba Corp 半導体記憶装置及び半導体集積回路
US6873539B1 (en) 2001-06-18 2005-03-29 Pierre Fazan Semiconductor device
US6912150B2 (en) 2003-05-13 2005-06-28 Lionel Portman Reference current generator, and method of programming, adjusting and/or operating same
JP2005191451A (ja) * 2003-12-26 2005-07-14 Toshiba Corp 半導体記憶装置
US6982918B2 (en) 2002-04-18 2006-01-03 Pierre Fazan Data storage device and refreshing method for use with such device
US7061050B2 (en) 2002-04-18 2006-06-13 Innovative Silicon S.A. Semiconductor device utilizing both fully and partially depleted devices
JP2006173291A (ja) * 2004-12-15 2006-06-29 Elpida Memory Inc 半導体チップ、その製造方法およびその用途
US7085156B2 (en) 2003-05-13 2006-08-01 Innovative Silicon S.A. Semiconductor memory device and method of operating same
US7085153B2 (en) 2003-05-13 2006-08-01 Innovative Silicon S.A. Semiconductor memory cell, array, architecture and device, and method of operating same
US7154151B2 (en) 2004-06-03 2006-12-26 Kabushiki Kaisha Toshiba Semiconductor device
JP2007018588A (ja) * 2005-07-06 2007-01-25 Toshiba Corp 半導体記憶装置および半導体記憶装置の駆動方法
US7177175B2 (en) 2003-09-24 2007-02-13 Innovative Silicon S.A. Low power programming technique for a floating body memory transistor, memory cell, and memory array
JP2007505436A (ja) * 2003-09-10 2007-03-08 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 耐欠陥性及び耐故障性回路相互接続
JP2007073754A (ja) * 2005-09-07 2007-03-22 Toshiba Corp 半導体装置
US7208799B2 (en) 2003-11-21 2007-04-24 Kabushiki Kaisha Toshiba Floating body cell dynamic random access memory with optimized body geometry
US7251164B2 (en) 2004-11-10 2007-07-31 Innovative Silicon S.A. Circuitry for and method of improving statistical distribution of integrated circuits
JP2007194259A (ja) * 2006-01-17 2007-08-02 Toshiba Corp 半導体装置及びその製造方法
JP2007242950A (ja) * 2006-03-09 2007-09-20 Toshiba Corp 半導体記憶装置
US7301838B2 (en) 2004-12-13 2007-11-27 Innovative Silicon S.A. Sense amplifier circuitry and architecture to write data into and/or read from memory cells
US7301803B2 (en) 2004-12-22 2007-11-27 Innovative Silicon S.A. Bipolar reading technique for a memory cell having an electrically floating body transistor
US7335934B2 (en) 2003-07-22 2008-02-26 Innovative Silicon S.A. Integrated circuit device, and method of fabricating same
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US7542340B2 (en) 2006-07-11 2009-06-02 Innovative Silicon Isi Sa Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
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JP2009177080A (ja) * 2008-01-28 2009-08-06 Toshiba Corp 半導体記憶装置
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US6617651B2 (en) 2003-09-09
US20040026749A1 (en) 2004-02-12
US20030015757A1 (en) 2003-01-23
CN1399340A (zh) 2003-02-26
KR20030011512A (ko) 2003-02-11
CN1217415C (zh) 2005-08-31
US6897531B2 (en) 2005-05-24
KR100440188B1 (ko) 2004-07-14
EP1280205A3 (en) 2009-10-07

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