ES2171616T3 - Procedimiento para la produccion de un substrato semiconductor. - Google Patents
Procedimiento para la produccion de un substrato semiconductor.Info
- Publication number
- ES2171616T3 ES2171616T3 ES96305134T ES96305134T ES2171616T3 ES 2171616 T3 ES2171616 T3 ES 2171616T3 ES 96305134 T ES96305134 T ES 96305134T ES 96305134 T ES96305134 T ES 96305134T ES 2171616 T3 ES2171616 T3 ES 2171616T3
- Authority
- ES
- Spain
- Prior art keywords
- silicon
- layer
- substrate
- porous
- production
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/0203—Making porous regions on the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Weting (AREA)
- Pressure Sensors (AREA)
Abstract
SE PROPORCIONA UN PROCESO PARA LA PRODUCCION DE UN SUSTRATO SEMICONDUCTOR EN EL QUE SE PROPORCIONA UN PRIMER SUSTRATO HECHO DE SILICIO QUE TIENE UNA CAPA DE SILICIO POROSO FORMADA SOBRE EL MISMO, HACIENDO POROSO EL SILICIO DEL SUBSTRATO Y UNA CAPA DE SILICIO MONOCRISTALINO NO POROSO, RECRECIDA DE MODO EPITAXIAL EN LA CAPA DE SILICIO POROSO, DESPUES SE LAMINA EL PRIMER SUSTRATO SOBRE UN SEGUNDO SUSTRATO EN UN ESTADO EN EL QUE AL MENOS UNA DE LAS CARAS DE LAMINACION DEL PRIMER Y DEL SEGUNDO SUSTRATO TENGA UNA CAPA DE OXIDO DE SILICIO Y LA CAPA DE SILICIO MONOCRISTALINO NO POROSO SE INTERPONGA ENTRE LOS SUSTRATOS LAMINADOS, Y FINALMENTE SE ELIMINA LA CAPA DE SILICIO POROSO MEDIANTE DECAPADO EN EL QUE LA CAPA DE SILICIO POROSO SE ELIMINA MEDIANTE UNA SOLUCION DE ATAQUE QUE DECAPE LA CAPA DE SILICIO MONOCRISTALINO NO POROSO Y LA CAPA DE OXIDO DE SILICIO A INDICES DE DECAPADO NO SUPERIORES A 10 ANGSTROMS POR MINUTO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17718995 | 1995-07-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2171616T3 true ES2171616T3 (es) | 2002-09-16 |
Family
ID=16026741
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES96305134T Expired - Lifetime ES2171616T3 (es) | 1995-07-13 | 1996-07-12 | Procedimiento para la produccion de un substrato semiconductor. |
Country Status (9)
Country | Link |
---|---|
US (1) | US6103598A (es) |
EP (1) | EP0753886B1 (es) |
KR (1) | KR100249456B1 (es) |
CN (1) | CN1058354C (es) |
DE (1) | DE69619602T2 (es) |
ES (1) | ES2171616T3 (es) |
MY (1) | MY113920A (es) |
SG (1) | SG66317A1 (es) |
TW (1) | TW317645B (es) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7148119B1 (en) | 1994-03-10 | 2006-12-12 | Canon Kabushiki Kaisha | Process for production of semiconductor substrate |
US20030087503A1 (en) * | 1994-03-10 | 2003-05-08 | Canon Kabushiki Kaisha | Process for production of semiconductor substrate |
JP3293736B2 (ja) * | 1996-02-28 | 2002-06-17 | キヤノン株式会社 | 半導体基板の作製方法および貼り合わせ基体 |
KR970052020A (ko) * | 1995-12-30 | 1997-07-29 | 김주용 | 에스 오 아이 기판 제조방법 |
KR100304161B1 (ko) | 1996-12-18 | 2001-11-30 | 미다라이 후지오 | 반도체부재의제조방법 |
SG71094A1 (en) * | 1997-03-26 | 2000-03-21 | Canon Kk | Thin film formation using laser beam heating to separate layers |
JP3847935B2 (ja) * | 1998-01-09 | 2006-11-22 | キヤノン株式会社 | 多孔質領域の除去方法及び半導体基体の製造方法 |
JP3218564B2 (ja) * | 1998-01-14 | 2001-10-15 | キヤノン株式会社 | 多孔質領域の除去方法及び半導体基体の製造方法 |
US6376285B1 (en) * | 1998-05-28 | 2002-04-23 | Texas Instruments Incorporated | Annealed porous silicon with epitaxial layer for SOI |
US20020106874A1 (en) * | 1998-07-03 | 2002-08-08 | Masaaki Iwane | Crystal growth process, semiconductor device, and its production process |
JP2000173976A (ja) * | 1998-12-02 | 2000-06-23 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2000223682A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基体の処理方法及び半導体基板の製造方法 |
US6410436B2 (en) * | 1999-03-26 | 2002-06-25 | Canon Kabushiki Kaisha | Method of cleaning porous body, and process for producing porous body, non-porous film or bonded substrate |
US8507361B2 (en) * | 2000-11-27 | 2013-08-13 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US6699770B2 (en) * | 2001-03-01 | 2004-03-02 | John Tarje Torvik | Method of making a hybride substrate having a thin silicon carbide membrane layer |
DE10128719A1 (de) * | 2001-06-13 | 2002-12-19 | Muehlbauer Ernst Gmbh & Co Kg | Zahnärztlicher Abformlöffel |
US7535100B2 (en) * | 2002-07-12 | 2009-05-19 | The United States Of America As Represented By The Secretary Of The Navy | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
JP2004103600A (ja) * | 2002-09-04 | 2004-04-02 | Canon Inc | 基板及びその製造方法 |
EP1396883A3 (en) * | 2002-09-04 | 2005-11-30 | Canon Kabushiki Kaisha | Substrate and manufacturing method therefor |
JP2004103855A (ja) * | 2002-09-10 | 2004-04-02 | Canon Inc | 基板及びその製造方法 |
JP2004103946A (ja) * | 2002-09-11 | 2004-04-02 | Canon Inc | 基板及びその製造方法 |
DE60310026D1 (de) * | 2003-01-24 | 2007-01-11 | St Microelectronics Srl | Pipeline Analog-Digital-Wandler mit Korrektion von Verstärkungsfehlern zwischen den Stufen |
US7198974B2 (en) * | 2003-03-05 | 2007-04-03 | Micron Technology, Inc. | Micro-mechanically strained semiconductor film |
US7220656B2 (en) * | 2003-04-29 | 2007-05-22 | Micron Technology, Inc. | Strained semiconductor by wafer bonding with misorientation |
US7115480B2 (en) * | 2003-05-07 | 2006-10-03 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
US7662701B2 (en) | 2003-05-21 | 2010-02-16 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
US7273788B2 (en) | 2003-05-21 | 2007-09-25 | Micron Technology, Inc. | Ultra-thin semiconductors bonded on glass substrates |
US7008854B2 (en) * | 2003-05-21 | 2006-03-07 | Micron Technology, Inc. | Silicon oxycarbide substrates for bonded silicon on insulator |
US7439158B2 (en) | 2003-07-21 | 2008-10-21 | Micron Technology, Inc. | Strained semiconductor by full wafer bonding |
US7153753B2 (en) | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20050132332A1 (en) * | 2003-12-12 | 2005-06-16 | Abhay Sathe | Multi-location coordinated test apparatus |
US7354863B2 (en) * | 2004-03-19 | 2008-04-08 | Micron Technology, Inc. | Methods of selectively removing silicon |
US7544584B2 (en) | 2006-02-16 | 2009-06-09 | Micron Technology, Inc. | Localized compressive strained semiconductor |
EP1926132A1 (en) * | 2006-11-23 | 2008-05-28 | S.O.I.Tec Silicon on Insulator Technologies | Chromium-free etching solution for Si-substrates and SiGe-substrates, method for revealing defects using the etching solution and process for treating Si-substrates and SiGe-substrates using the etching solution |
CN100440489C (zh) * | 2006-11-28 | 2008-12-03 | 北京大学 | 一种多孔硅片及其制备方法 |
RU2461090C1 (ru) * | 2010-12-23 | 2012-09-10 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Способ изготовления полупроводниковой структуры |
CN102169552A (zh) * | 2011-01-28 | 2011-08-31 | 上海集成电路研发中心有限公司 | 射频识别标签及其制造方法 |
US20190131454A1 (en) * | 2017-11-01 | 2019-05-02 | Qualcomm Incorporated | Semiconductor device with strained silicon layers on porous silicon |
TWI683351B (zh) * | 2017-12-14 | 2020-01-21 | 新唐科技股份有限公司 | 半導體裝置及其形成方法 |
WO2020245423A1 (en) * | 2019-06-06 | 2020-12-10 | Iqe Plc | Tunable stress compensation in layered structures |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2660064B2 (ja) * | 1988-10-02 | 1997-10-08 | キヤノン株式会社 | 結晶物品及びその形成方法 |
US5190613A (en) * | 1988-10-02 | 1993-03-02 | Canon Kabushiki Kaisha | Method for forming crystals |
US5290712A (en) * | 1989-03-31 | 1994-03-01 | Canon Kabushiki Kaisha | Process for forming crystalline semiconductor film |
JPH03215391A (ja) * | 1989-06-26 | 1991-09-20 | Canon Inc | 結晶の成長方法 |
US5278092A (en) * | 1989-08-07 | 1994-01-11 | Canon Kabushiki Kaisha | Method of forming crystal semiconductor film |
US5278093A (en) * | 1989-09-23 | 1994-01-11 | Canon Kabushiki Kaisha | Method for forming semiconductor thin film |
JP2695488B2 (ja) * | 1989-10-09 | 1997-12-24 | キヤノン株式会社 | 結晶の成長方法 |
US5363793A (en) * | 1990-04-06 | 1994-11-15 | Canon Kabushiki Kaisha | Method for forming crystals |
ATE259098T1 (de) * | 1990-08-03 | 2004-02-15 | Canon Kk | Verfahren zur herstellung eines soi-substrats |
JP2608351B2 (ja) * | 1990-08-03 | 1997-05-07 | キヤノン株式会社 | 半導体部材及び半導体部材の製造方法 |
US5403751A (en) * | 1990-11-29 | 1995-04-04 | Canon Kabushiki Kaisha | Process for producing a thin silicon solar cell |
US5403771A (en) * | 1990-12-26 | 1995-04-04 | Canon Kabushiki Kaisha | Process for producing a solar cell by means of epitaxial growth process |
JP3347354B2 (ja) * | 1991-02-15 | 2002-11-20 | キヤノン株式会社 | エッチング方法および半導体基材の作製方法 |
SG93197A1 (en) * | 1991-02-15 | 2002-12-17 | Canon Kk | Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution |
TW211621B (es) * | 1991-07-31 | 1993-08-21 | Canon Kk | |
EP1043768B1 (en) * | 1992-01-30 | 2004-09-08 | Canon Kabushiki Kaisha | Process for producing semiconductor substrates |
JP3261685B2 (ja) * | 1992-01-31 | 2002-03-04 | キヤノン株式会社 | 半導体素子基体及びその作製方法 |
-
1996
- 1996-07-11 US US08/678,694 patent/US6103598A/en not_active Expired - Lifetime
- 1996-07-12 CN CN96111711A patent/CN1058354C/zh not_active Expired - Fee Related
- 1996-07-12 TW TW085108482A patent/TW317645B/zh not_active IP Right Cessation
- 1996-07-12 EP EP96305134A patent/EP0753886B1/en not_active Expired - Lifetime
- 1996-07-12 ES ES96305134T patent/ES2171616T3/es not_active Expired - Lifetime
- 1996-07-12 DE DE69619602T patent/DE69619602T2/de not_active Expired - Lifetime
- 1996-07-12 MY MYPI96002881A patent/MY113920A/en unknown
- 1996-07-13 SG SG1996010249A patent/SG66317A1/en unknown
- 1996-07-13 KR KR1019960028307A patent/KR100249456B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1058354C (zh) | 2000-11-08 |
TW317645B (es) | 1997-10-11 |
DE69619602D1 (de) | 2002-04-11 |
EP0753886A1 (en) | 1997-01-15 |
DE69619602T2 (de) | 2002-08-08 |
SG66317A1 (en) | 1999-07-20 |
US6103598A (en) | 2000-08-15 |
EP0753886B1 (en) | 2002-03-06 |
CN1149758A (zh) | 1997-05-14 |
KR100249456B1 (ko) | 2000-03-15 |
MY113920A (en) | 2002-06-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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