DE3856075D1 - Verfahren zur herstellung dünner einzelkristallsiliciuminseln auf einem isolator - Google Patents

Verfahren zur herstellung dünner einzelkristallsiliciuminseln auf einem isolator

Info

Publication number
DE3856075D1
DE3856075D1 DE3856075T DE3856075T DE3856075D1 DE 3856075 D1 DE3856075 D1 DE 3856075D1 DE 3856075 T DE3856075 T DE 3856075T DE 3856075 T DE3856075 T DE 3856075T DE 3856075 D1 DE3856075 D1 DE 3856075D1
Authority
DE
Germany
Prior art keywords
isolator
single crystal
crystal silicon
thin single
producing thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3856075T
Other languages
English (en)
Other versions
DE3856075T2 (de
Inventor
Philip Shiota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3856075D1 publication Critical patent/DE3856075D1/de
Publication of DE3856075T2 publication Critical patent/DE3856075T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE3856075T 1987-01-27 1988-01-26 Verfahren zur herstellung dünner einzelkristallsiliciuminseln auf einem isolator Expired - Fee Related DE3856075T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US731287A 1987-01-27 1987-01-27
US07/147,892 US5086011A (en) 1987-01-27 1988-01-25 Process for producing thin single crystal silicon islands on insulator
PCT/US1988/000241 WO1988005600A1 (en) 1987-01-27 1988-01-26 Process for producing thin single crystal silicon islands on insulator

Publications (2)

Publication Number Publication Date
DE3856075D1 true DE3856075D1 (de) 1998-01-08
DE3856075T2 DE3856075T2 (de) 1998-12-24

Family

ID=26676819

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3856075T Expired - Fee Related DE3856075T2 (de) 1987-01-27 1988-01-26 Verfahren zur herstellung dünner einzelkristallsiliciuminseln auf einem isolator

Country Status (6)

Country Link
US (1) US5086011A (de)
EP (1) EP0299062B1 (de)
JP (1) JP2717979B2 (de)
AT (1) ATE160651T1 (de)
DE (1) DE3856075T2 (de)
WO (1) WO1988005600A1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248524A (ja) * 1988-03-30 1989-10-04 Hitachi Ltd 半導体装置とその製造方法
JPH03296247A (ja) * 1990-04-13 1991-12-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5395788A (en) * 1991-03-15 1995-03-07 Shin Etsu Handotai Co., Ltd. Method of producing semiconductor substrate
US5344785A (en) * 1992-03-13 1994-09-06 United Technologies Corporation Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate
US5234868A (en) * 1992-10-29 1993-08-10 International Business Machines Corporation Method for determining planarization endpoint during chemical-mechanical polishing
US5264395A (en) * 1992-12-16 1993-11-23 International Business Machines Corporation Thin SOI layer for fully depleted field effect transistors
US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
US5399231A (en) * 1993-10-18 1995-03-21 Regents Of The University Of California Method of forming crystalline silicon devices on glass
US5500279A (en) * 1994-08-26 1996-03-19 Eastman Kodak Company Laminated metal structure and metod of making same
US5591300A (en) * 1995-06-07 1997-01-07 Vtc Inc. Single crystal silicon dry-etch endpoint based on dopant-dependent and thermally-assisted etch rates
US6649977B1 (en) 1995-09-11 2003-11-18 The Regents Of The University Of California Silicon on insulator self-aligned transistors
US5681775A (en) * 1995-11-15 1997-10-28 International Business Machines Corporation Soi fabrication process
US5672242A (en) * 1996-01-31 1997-09-30 Integrated Device Technology, Inc. High selectivity nitride to oxide etch process
US6093331A (en) * 1997-12-11 2000-07-25 Advanced Micro Devices, Inc. Backside silicon removal for face down chip analysis
US6428718B1 (en) 1999-08-26 2002-08-06 Advanced Micro Devices, Inc. Selective back side wet etch
US6294395B1 (en) 1999-08-26 2001-09-25 Advanced Micro Devices, Inc. Back side reactive ion etch
US6355564B1 (en) 1999-08-26 2002-03-12 Advanced Micro Devices, Inc. Selective back side reactive ion etch
US6555891B1 (en) 2000-10-17 2003-04-29 International Business Machines Corporation SOI hybrid structure with selective epitaxial growth of silicon
US6838294B2 (en) * 2002-02-13 2005-01-04 Intel Corporation Focused ion beam visual endpointing
JP2004103600A (ja) * 2002-09-04 2004-04-02 Canon Inc 基板及びその製造方法
TWI242796B (en) * 2002-09-04 2005-11-01 Canon Kk Substrate and manufacturing method therefor
JP2004103855A (ja) * 2002-09-10 2004-04-02 Canon Inc 基板及びその製造方法
JP2004103946A (ja) * 2002-09-11 2004-04-02 Canon Inc 基板及びその製造方法
FR2852143B1 (fr) * 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
KR100487927B1 (ko) * 2003-07-21 2005-05-09 주식회사 하이닉스반도체 마그네틱 램의 형성방법
US7547605B2 (en) * 2004-11-22 2009-06-16 Taiwan Semiconductor Manufacturing Company Microelectronic device and a method for its manufacture
US20230056416A1 (en) * 2021-08-23 2023-02-23 Palo Alto Research Center Incorporated Process of transferring of vcsel epi layer onto metal host substrate

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3769562A (en) * 1972-02-07 1973-10-30 Texas Instruments Inc Double isolation for electronic devices
US3909332A (en) * 1973-06-04 1975-09-30 Gen Electric Bonding process for dielectric isolation of single crystal semiconductor structures
JPS5066185A (de) * 1973-10-12 1975-06-04
FR2262406B1 (de) * 1974-02-26 1982-02-19 Rodriguez Valentin
US3997381A (en) * 1975-01-10 1976-12-14 Intel Corporation Method of manufacture of an epitaxial semiconductor layer on an insulating substrate
US3974006A (en) * 1975-03-21 1976-08-10 Valentin Rodriguez Method of obtaining high temperature resistant assemblies comprising isolated silicon islands bonded to a substrate
JPS58151027A (ja) * 1982-03-03 1983-09-08 Hitachi Ltd エツチング方法
JPS60262438A (ja) * 1984-06-08 1985-12-25 Matsushita Electronics Corp 半導体装置の製造方法
JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
JPS6173345A (ja) * 1984-09-19 1986-04-15 Toshiba Corp 半導体装置
US4599247A (en) * 1985-01-04 1986-07-08 Texas Instruments Incorporated Semiconductor processing facility for providing enhanced oxidation rate
JPS61289643A (ja) * 1985-06-18 1986-12-19 Matsushita Electric Ind Co Ltd 半導体集積回路装置の製造方法
JPS61290737A (ja) * 1985-06-19 1986-12-20 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4648936A (en) * 1985-10-11 1987-03-10 The United States Of America As Represented By The United States Department Of Energy Dopant type and/or concentration selective dry photochemical etching of semiconductor materials
US4691779A (en) * 1986-01-17 1987-09-08 Halliburton Company Hydrostatic referenced safety-circulating valve

Also Published As

Publication number Publication date
WO1988005600A1 (en) 1988-07-28
ATE160651T1 (de) 1997-12-15
EP0299062B1 (de) 1997-11-26
EP0299062A1 (de) 1989-01-18
EP0299062A4 (en) 1991-03-20
DE3856075T2 (de) 1998-12-24
US5086011A (en) 1992-02-04
JPH01503026A (ja) 1989-10-12
JP2717979B2 (ja) 1998-02-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee