KR920003408A - 반도체 기판의 제조 방법 - Google Patents

반도체 기판의 제조 방법 Download PDF

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Publication number
KR920003408A
KR920003408A KR1019910011309A KR910011309A KR920003408A KR 920003408 A KR920003408 A KR 920003408A KR 1019910011309 A KR1019910011309 A KR 1019910011309A KR 910011309 A KR910011309 A KR 910011309A KR 920003408 A KR920003408 A KR 920003408A
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KR
South Korea
Prior art keywords
semiconductor substrate
semiconductor
layer
manufacturing
mirror
Prior art date
Application number
KR1019910011309A
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English (en)
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KR940010159B1 (ko
Inventor
다다히데 호시
Original Assignee
아오이 죠이찌
가부시끼가이샤 도시바
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Publication of KR920003408A publication Critical patent/KR920003408A/ko
Application granted granted Critical
Publication of KR940010159B1 publication Critical patent/KR940010159B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Abstract

내용 없음.

Description

반도체 기판의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 한 실시예를 도시한 공정도,
제 2 도는 제 1 도에 관한 반도체층의 층 두께 분포를 도시한 분포도.
제 3 도는 유전체 분리 구조를 갖는 반도체 장치를 도시한 단면도.
제 4 도는 종래예를 도시한 공정도.
제 5 도는 비교예에 있어서의 층 두께 분포를 도시한 분포도.
* 도면의 주요부분에 대한 부호의 설명
25 : 제 1 실리콘 기판(제 1 반도체 기판)
27 : 제 2 실리콘 기판(제 2 반도체 기판) 29 : 제 2 유전체층(유전체층)
30 : 반도체층

Claims (1)

  1. 제1및 제2반도체 기판(25 및 27)의 경면 가공된 각 한쪽 면을 서로 밀착한 후에, 상기 제1반도체기판의 다른쪽 면을 거칠게 연삭하고, 그 후 가공 왜곡 제거 에칭하며, 이어서 상기 제1반도체 기판의 다른쪽 면을 연마해서 첩착부와의 사이에 소정 두께의 반도체층(30)을 형성할 때 상기 제1반도체 기판의 다른쪽면을 경면 연마해서 첩착부와의 사이에 소정 두께의 반도체층(30)을 형성할 때 상기 제 1 반도체 기판의 다른쪽 면상에 유전체층(29)를 설치해서 가공 왜곡 제거 에칭을 행하는 것을 특징으로 하는 반도체 기판의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910011309A 1990-07-05 1991-07-04 반도체 기판의 제조 방법 KR940010159B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2177883A JP2721265B2 (ja) 1990-07-05 1990-07-05 半導体基板の製造方法
JP2-177883 1990-07-05

Publications (2)

Publication Number Publication Date
KR920003408A true KR920003408A (ko) 1992-02-29
KR940010159B1 KR940010159B1 (ko) 1994-10-22

Family

ID=16038725

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910011309A KR940010159B1 (ko) 1990-07-05 1991-07-04 반도체 기판의 제조 방법

Country Status (3)

Country Link
EP (1) EP0464837A3 (ko)
JP (1) JP2721265B2 (ko)
KR (1) KR940010159B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4204436A1 (de) * 1992-02-14 1993-08-19 Daimler Benz Ag Verfahren zur herstellung von halbleiterbauelementen aus duennen folien
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
DE69332407T2 (de) * 1992-06-17 2003-06-18 Harris Corp Herstellung von Halbleiteranordnungen auf SOI substraten
JPH06112451A (ja) * 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Ｓｏｉ基板の製造方法
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP5221279B2 (ja) * 2008-10-22 2013-06-26 株式会社ディスコ 積層デバイスの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6173345A (ja) * 1984-09-19 1986-04-15 Toshiba Corp 半導体装置
JPS63314844A (ja) * 1987-06-18 1988-12-22 Toshiba Corp 半導体装置の製造方法
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding
JPH084126B2 (ja) * 1987-09-19 1996-01-17 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR940010159B1 (ko) 1994-10-22
EP0464837A2 (en) 1992-01-08
JPH0465126A (ja) 1992-03-02
JP2721265B2 (ja) 1998-03-04
EP0464837A3 (en) 1993-01-27

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