EP0464837A3 - Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure - Google Patents

Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure Download PDF

Info

Publication number
EP0464837A3
EP0464837A3 EP19910111196 EP91111196A EP0464837A3 EP 0464837 A3 EP0464837 A3 EP 0464837A3 EP 19910111196 EP19910111196 EP 19910111196 EP 91111196 A EP91111196 A EP 91111196A EP 0464837 A3 EP0464837 A3 EP 0464837A3
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
separation structure
dielectric separation
semiconductor substrate
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910111196
Other languages
English (en)
Other versions
EP0464837A2 (en
Inventor
Tadahide Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0464837A2 publication Critical patent/EP0464837A2/en
Publication of EP0464837A3 publication Critical patent/EP0464837A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
EP19910111196 1990-07-05 1991-07-05 Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure Withdrawn EP0464837A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2177883A JP2721265B2 (ja) 1990-07-05 1990-07-05 半導体基板の製造方法
JP177883/90 1990-07-05

Publications (2)

Publication Number Publication Date
EP0464837A2 EP0464837A2 (en) 1992-01-08
EP0464837A3 true EP0464837A3 (en) 1993-01-27

Family

ID=16038725

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910111196 Withdrawn EP0464837A3 (en) 1990-07-05 1991-07-05 Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure

Country Status (3)

Country Link
EP (1) EP0464837A3 (ko)
JP (1) JP2721265B2 (ko)
KR (1) KR940010159B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4204436A1 (de) * 1992-02-14 1993-08-19 Daimler Benz Ag Verfahren zur herstellung von halbleiterbauelementen aus duennen folien
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
DE69332407T2 (de) * 1992-06-17 2003-06-18 Harris Corp Herstellung von Halbleiteranordnungen auf SOI substraten
JPH06112451A (ja) * 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Ｓｏｉ基板の製造方法
FR2777115B1 (fr) 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP5221279B2 (ja) * 2008-10-22 2013-06-26 株式会社ディスコ 積層デバイスの製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182032A2 (en) * 1984-09-19 1986-05-28 Kabushiki Kaisha Toshiba SoI semiconductor device and method for producing it
EP0296754A2 (en) * 1987-06-18 1988-12-28 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having a trench isolation region,
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH084126B2 (ja) * 1987-09-19 1996-01-17 富士通株式会社 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182032A2 (en) * 1984-09-19 1986-05-28 Kabushiki Kaisha Toshiba SoI semiconductor device and method for producing it
EP0296754A2 (en) * 1987-06-18 1988-12-28 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having a trench isolation region,
US4851078A (en) * 1987-06-29 1989-07-25 Harris Corporation Dielectric isolation process using double wafer bonding

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GOTOU H., ET AL.: "SOI-DEVICE ON BONDED WAFER.", FUJITSU-SCIENTIFIC AND TECHNICAL JOURNAL., FUJITSU LTD., JP, vol. 24., no. 04 + INDEX., 21 December 1988 (1988-12-21), JP, pages 408 - 417., XP000112818, ISSN: 0016-2523 *

Also Published As

Publication number Publication date
EP0464837A2 (en) 1992-01-08
JP2721265B2 (ja) 1998-03-04
JPH0465126A (ja) 1992-03-02
KR920003408A (ko) 1992-02-29
KR940010159B1 (ko) 1994-10-22

Similar Documents

Publication Publication Date Title
KR100199259B1 (en) Fabrication method of semiconductor integrated circuit device
EP0489179A4 (en) Method of manufacturing semiconductor integrated circuit and equipment for the manufacture
EP0423722A3 (en) Method of making complete dielectric isolation structure in semiconductor integrated circuit
EP0465044A3 (en) Method of etching for integrated circuits with planarized dielectric
GB2128024B (en) Method of manufacturing semiconductor integrated circuit device
GB2241607B (en) Method of planarizing a dielectric formed over a semiconductor substrate
DE3380837D1 (en) Isolated dielectric structure for integrated circuits and method for fabricating such structure
GB2150349B (en) Process of fabricating semiconductor integrated circuit device
EP0092871A3 (en) Semiconductor integrated circuits and method of manufacturing
JPS56140646A (en) Method of manufacturing semiconductor circuit on semiconductor silicon substrate
EP0556795A3 (en) Method of manufacturing substrate having semiconductor on insulator
GB2228619B (en) Method of fabricating semiconductor integrated circuits
HK69587A (en) Semiconductor integrated circuit devices and method of manufacturing the same
GB8814823D0 (en) Vitreous substrate bearing electric circuit components & method of manufacturing same
EP0464837A3 (en) Method of manufacturing semiconductor substrate using semiconductor integrated circuit having dielectric separation structure
EP0239060A3 (en) Method for manufacturing semiconductor integrated circuits including cmos and high-voltage electronic devices
GB2148593B (en) Process for manufacturing the isolating regions of a semiconductor integrated circuit device
EP0488230A3 (en) Method of manufacturing a semiconductor substrate having a dielectric isolation structure
EP0360992A3 (en) A dielectric layer of first interconnection for electronic semiconductor devices
EP0469583A3 (en) Semiconductor substrate with complete dielectric isolation structure and method of making the same
EP0427328A3 (en) Method of manufacturing integrated circuits as well as integrated circuit
DE3279916D1 (en) Method of manufacturing integrated circuit devices using dielectric isolation
EP0450091A4 (en) Method of producing semiconductor integrated circuit devices
MY8700644A (en) Semiconductor integrated circuit devices and method of manufacturing the same
GB2193036B (en) Method of fabricating a semiconductor integrated circuit device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19910705

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 19930405

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19950825