KR970052020A - 에스 오 아이 기판 제조방법 - Google Patents

에스 오 아이 기판 제조방법 Download PDF

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Publication number
KR970052020A
KR970052020A KR1019950069452A KR19950069452A KR970052020A KR 970052020 A KR970052020 A KR 970052020A KR 1019950069452 A KR1019950069452 A KR 1019950069452A KR 19950069452 A KR19950069452 A KR 19950069452A KR 970052020 A KR970052020 A KR 970052020A
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KR
South Korea
Prior art keywords
layer
wafer
device isolation
isolation layer
semiconductor wafer
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Application number
KR1019950069452A
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English (en)
Inventor
김재갑
Original Assignee
김주용
현대전자산업 주식회사
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950069452A priority Critical patent/KR970052020A/ko
Priority to DE19653199A priority patent/DE19653199A1/de
Priority to TW085115676A priority patent/TW348302B/zh
Priority to JP8357090A priority patent/JPH1050824A/ja
Priority to GB9626980A priority patent/GB2309826B/en
Priority to CN96123936A priority patent/CN1078737C/zh
Publication of KR970052020A publication Critical patent/KR970052020A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

본 발명은 에스 오 아이 기판 제조방법에 관한 것으로, 보다 구체적으로 SOI의 기판의 접착 공정시 균일한 SOI층을 형성할 수 있는 SOI기판 제조방법에 관한 것으로, 본 발명에 의하면 SOI 기판에 소자 형성 영역인 SOI층의 에치백 공정시, 웨리퍼를 접착하기 이전 반도체 웨이퍼 내부에 소자 분리막을 기형성하여, 웨이퍼의 접착 후, 이 소자 분리막을 에치백 저지층으로 하여 식각을 진행하면, 표면이 균일한 SOI층을 형성하고, 이로써 소자의 제조 수율을 향상시킬 수 있다.

Description

에스 오 아이 기판 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (6)

  1. 반도체 웨이퍼상의 적소에 소자 분리막을 형성하는 단계; 상기 소자 분리막을 포함한 웨이퍼 상부에 절연막을 형성하는 단계; 상기 소자 분리막 및 절연막을 포함한 반도체 웨이퍼와 부착될 핸들링 웨이퍼를 준비하는 단계; 상기 소자 분리막과 절연막이 형성된 반도체 웨이퍼의 표면과 핸들링 웨이퍼가 접촉되도록 두 웨이퍼를 접착시키는 단계; 및 상기 반도체 웨이퍼의 표면을 상기 소자 분리막이 노출되도록 에치백하여 SOI층을 형성하는 단계를 포함하는 것을 특징으로 하는 SOI 기판 제조방법.
  2. 제1항에 있어서, 상기 절연막은 실리콘 산화막인 것을 특징으로 하는 SOI 기판 제조방법.
  3. 제1항에 있어서, 상기 핸들링 웨이퍼는 실리콘 웨이퍼이고, 표면에 일정 두께의 절연막이 형성되어 있는 것을 특징으로 하는 SOI 기판 제조방법.
  4. 제1항에 있어서, 소자 분리막은 선택적 산화 방식에 따른 로코스 산화막인 것을 특징으로 하는 SOI 기판 제조방법.
  5. 제1항에 있어서, 상기 소자 분리막은 상기 반도체 웨이퍼의 소자 분리 예정영역을 소정 깊이로 식각한 다음, 식각된 기판 내부를 절연막으로 충진하여 형성하는 트랜치 산화막인 것을 특징으로 하는 SOI 기판 제조방법.
  6. 제1항에 있어서, 상기 소자 분리막의 두께는 0.1 내지 0.5㎛인 것을 특징으로 하는 SOI 기판 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950069452A 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법 KR970052020A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019950069452A KR970052020A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법
DE19653199A DE19653199A1 (de) 1995-12-30 1996-12-19 Verfahren zur Herstellung eines Substrates mit Silicium auf einem Isolator
TW085115676A TW348302B (en) 1995-12-30 1996-12-19 Method of fabricating silicon-on-insulator substrate
JP8357090A JPH1050824A (ja) 1995-12-30 1996-12-26 Ｓｏｉ基板の製造方法
GB9626980A GB2309826B (en) 1995-12-30 1996-12-27 Method of fabricating silicon-on-insulator substrate
CN96123936A CN1078737C (zh) 1995-12-30 1996-12-30 Soi基片的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069452A KR970052020A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법

Publications (1)

Publication Number Publication Date
KR970052020A true KR970052020A (ko) 1997-07-29

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ID=19448450

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069452A KR970052020A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법

Country Status (6)

Country Link
JP (1) JPH1050824A (ko)
KR (1) KR970052020A (ko)
CN (1) CN1078737C (ko)
DE (1) DE19653199A1 (ko)
GB (1) GB2309826B (ko)
TW (1) TW348302B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010056788A (ko) * 1999-12-16 2001-07-04 박종섭 에스오아이 기판의 제조방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148183B (zh) * 2011-03-10 2015-04-29 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi的形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719839B2 (ja) * 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JPH03180070A (ja) * 1989-12-08 1991-08-06 Seiko Epson Corp 半導体装置及びその製造方法
JP2754819B2 (ja) * 1989-12-28 1998-05-20 株式会社日本自動車部品総合研究所 誘電体分離型半導体基板の製造方法
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
JP3099446B2 (ja) * 1991-08-30 2000-10-16 株式会社デンソー 誘電体分離領域を有する半導体基板
KR950000106B1 (ko) * 1992-01-08 1995-01-09 삼성전자 주식회사 반도체 장치의 제조방법
US6103598A (en) * 1995-07-13 2000-08-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010056788A (ko) * 1999-12-16 2001-07-04 박종섭 에스오아이 기판의 제조방법

Also Published As

Publication number Publication date
CN1162836A (zh) 1997-10-22
GB2309826B (en) 2000-07-05
DE19653199A1 (de) 1997-07-03
JPH1050824A (ja) 1998-02-20
GB2309826A (en) 1997-08-06
TW348302B (en) 1998-12-21
GB9626980D0 (en) 1997-02-12
CN1078737C (zh) 2002-01-30

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