CN1078737C - Soi基片的制造方法 - Google Patents

Soi基片的制造方法 Download PDF

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Publication number
CN1078737C
CN1078737C CN96123936A CN96123936A CN1078737C CN 1078737 C CN1078737 C CN 1078737C CN 96123936 A CN96123936 A CN 96123936A CN 96123936 A CN96123936 A CN 96123936A CN 1078737 C CN1078737 C CN 1078737C
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CN
China
Prior art keywords
silicon chip
silicon
film
separation membrane
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN96123936A
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English (en)
Chinese (zh)
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CN1162836A (zh
Inventor
金载甲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MagnaChip Semiconductor Ltd
Original Assignee
Hyundai Electronics Industries Co Ltd
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Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1162836A publication Critical patent/CN1162836A/zh
Application granted granted Critical
Publication of CN1078737C publication Critical patent/CN1078737C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
CN96123936A 1995-12-30 1996-12-30 Soi基片的制造方法 Expired - Lifetime CN1078737C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR69452/95 1995-12-30
KR1019950069452A KR970052020A (ko) 1995-12-30 1995-12-30 에스 오 아이 기판 제조방법

Publications (2)

Publication Number Publication Date
CN1162836A CN1162836A (zh) 1997-10-22
CN1078737C true CN1078737C (zh) 2002-01-30

Family

ID=19448450

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96123936A Expired - Lifetime CN1078737C (zh) 1995-12-30 1996-12-30 Soi基片的制造方法

Country Status (6)

Country Link
JP (1) JPH1050824A (ko)
KR (1) KR970052020A (ko)
CN (1) CN1078737C (ko)
DE (1) DE19653199A1 (ko)
GB (1) GB2309826B (ko)
TW (1) TW348302B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010056788A (ko) * 1999-12-16 2001-07-04 박종섭 에스오아이 기판의 제조방법
CN102148183B (zh) * 2011-03-10 2015-04-29 上海华虹宏力半导体制造有限公司 具有阶梯型氧化埋层的soi的形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area
US5138421A (en) * 1989-10-18 1992-08-11 Kabushiki Kaisha Toshiba Semiconductor substrate and method of producing the same, and semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03180070A (ja) * 1989-12-08 1991-08-06 Seiko Epson Corp 半導体装置及びその製造方法
JP2754819B2 (ja) * 1989-12-28 1998-05-20 株式会社日本自動車部品総合研究所 誘電体分離型半導体基板の製造方法
JP3099446B2 (ja) * 1991-08-30 2000-10-16 株式会社デンソー 誘電体分離領域を有する半導体基板
KR950000106B1 (ko) * 1992-01-08 1995-01-09 삼성전자 주식회사 반도체 장치의 제조방법
US6103598A (en) * 1995-07-13 2000-08-15 Canon Kabushiki Kaisha Process for producing semiconductor substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138421A (en) * 1989-10-18 1992-08-11 Kabushiki Kaisha Toshiba Semiconductor substrate and method of producing the same, and semiconductor device
US5091330A (en) * 1990-12-28 1992-02-25 Motorola, Inc. Method of fabricating a dielectric isolated area

Also Published As

Publication number Publication date
CN1162836A (zh) 1997-10-22
GB2309826B (en) 2000-07-05
DE19653199A1 (de) 1997-07-03
JPH1050824A (ja) 1998-02-20
GB2309826A (en) 1997-08-06
KR970052020A (ko) 1997-07-29
TW348302B (en) 1998-12-21
GB9626980D0 (en) 1997-02-12

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Owner name: HYNIX SEMICONDUCTOR INC.

Free format text: FORMER NAME OR ADDRESS: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD.

CP03 "change of name, title or address"

Address after: Gyeonggi Do, South Korea

Patentee after: Hairyoksa Semiconductor Co., Ltd.

Address before: Gyeonggi Do, South Korea

Patentee before: Hyundai Electronics Industries Co., Ltd.

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Owner name: MAGNACHIP CO., LTD.

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Effective date: 20070601

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Address after: North Chungcheong Province

Patentee after: Magnachip Semiconductor Ltd.

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Patentee before: Hairyoksa Semiconductor Co., Ltd.

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Granted publication date: 20020130

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