KR920007104A - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
- Publication number
- KR920007104A KR920007104A KR1019910014294A KR910014294A KR920007104A KR 920007104 A KR920007104 A KR 920007104A KR 1019910014294 A KR1019910014294 A KR 1019910014294A KR 910014294 A KR910014294 A KR 910014294A KR 920007104 A KR920007104 A KR 920007104A
- Authority
- KR
- South Korea
- Prior art keywords
- back surface
- grinding
- manufacturing
- semiconductor device
- gaas substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000003486 chemical etching Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 3
- 239000002245 particle Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Weting (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 반도체 소자의 제조방법의 1실시예의 특징 부분의 개략공정도
제2도는 숫돌입자직경과 마무리면 조도와의 관계를 표시한 도면
제3도는 에칭량과 이면의 표면상태계수와의 관계를 표시한 도면
* 도면의 주요부분에 대한 부호의 설명
1: 반도체 소자 형성공정 2: 기판의 이면연삭공정
3: 화학적에칭공정
Claims (1)
- GaAs 기판의 일평면상에 반도체 소자를 형성하는 소자형성공정과, 상기 GaAs 기판의 이면을 평균입자 직경이 6㎛ 이상의 숫돌을 사용해서 연삭하고, GaAs 기판을 소정의 두께로 하는 연삭공정과, 상기 연삭공정후, 상기 이면에 하등의 연삭처리를 실시하는 일없이, 그 이면을 화학적 에칭법에 의해 0.6㎛ 이상 에칭하는 공정을 포함하는 반도체 소자의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-235152 | 1990-09-05 | ||
JP2235152A JP2610703B2 (ja) | 1990-09-05 | 1990-09-05 | 半導体素子の製造方法 |
JP90-235152 | 1990-09-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920007104A true KR920007104A (ko) | 1992-04-28 |
KR940002915B1 KR940002915B1 (ko) | 1994-04-07 |
Family
ID=16981823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910014294A KR940002915B1 (ko) | 1990-09-05 | 1991-08-20 | 반도체 소자의 제조방법 |
Country Status (8)
Country | Link |
---|---|
US (1) | US5122481A (ko) |
EP (1) | EP0475259B1 (ko) |
JP (1) | JP2610703B2 (ko) |
KR (1) | KR940002915B1 (ko) |
AU (1) | AU649063B2 (ko) |
CA (1) | CA2050675A1 (ko) |
DE (1) | DE69112545T2 (ko) |
DK (1) | DK0475259T3 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023132518A1 (ko) * | 2022-01-10 | 2023-07-13 | 도레이첨단소재 주식회사 | 고강도 메타 아라미드 섬유 및 그의 제조방법 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279704A (en) * | 1991-04-23 | 1994-01-18 | Honda Giken Kogyo Kabushiki Kaisha | Method of fabricating semiconductor device |
US5245794A (en) * | 1992-04-09 | 1993-09-21 | Advanced Micro Devices, Inc. | Audio end point detector for chemical-mechanical polishing and method therefor |
US5268065A (en) * | 1992-12-21 | 1993-12-07 | Motorola, Inc. | Method for thinning a semiconductor wafer |
US5480842A (en) * | 1994-04-11 | 1996-01-02 | At&T Corp. | Method for fabricating thin, strong, and flexible die for smart cards |
JPH0817777A (ja) * | 1994-07-01 | 1996-01-19 | Mitsubishi Materials Shilicon Corp | シリコンウェーハの洗浄方法 |
US5691248A (en) * | 1995-07-26 | 1997-11-25 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
US5648684A (en) * | 1995-07-26 | 1997-07-15 | International Business Machines Corporation | Endcap chip with conductive, monolithic L-connect for multichip stack |
US6059637A (en) * | 1997-12-15 | 2000-05-09 | Lsi Logic Corporation | Process for abrasive removal of copper from the back surface of a silicon substrate |
DE19921230B4 (de) * | 1999-05-07 | 2009-04-02 | Giesecke & Devrient Gmbh | Verfahren zum Handhaben von gedünnten Chips zum Einbringen in Chipkarten |
US6560871B1 (en) * | 2000-03-21 | 2003-05-13 | Hewlett-Packard Development Company, L.P. | Semiconductor substrate having increased facture strength and method of forming the same |
KR100467009B1 (ko) * | 2000-08-04 | 2005-01-24 | 샤프 가부시키가이샤 | 반도체 웨이퍼 표면의 오염을 방지할 수 있는 반도체웨이퍼의 박층화 방법 및 반도체 웨이퍼의 이면 연삭장치 |
CN100355031C (zh) | 2002-03-12 | 2007-12-12 | 浜松光子学株式会社 | 基板的分割方法 |
JP4544876B2 (ja) * | 2003-02-25 | 2010-09-15 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2005005380A (ja) * | 2003-06-10 | 2005-01-06 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2005026314A (ja) * | 2003-06-30 | 2005-01-27 | Sanyo Electric Co Ltd | 固体撮像素子の製造方法 |
JP2005303218A (ja) * | 2004-04-16 | 2005-10-27 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP4872208B2 (ja) * | 2004-11-18 | 2012-02-08 | 富士電機株式会社 | 半導体装置の製造方法 |
JP5149020B2 (ja) * | 2008-01-23 | 2013-02-20 | 株式会社ディスコ | ウエーハの研削方法 |
GB2459301B (en) * | 2008-04-18 | 2011-09-14 | Xsil Technology Ltd | A method of dicing wafers to give high die strength |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SU393073A1 (ru) * | 1970-12-04 | 1973-08-10 | Способ повышения долговечности алмазных, например выглаживающих инструментов | |
AU527845B2 (en) * | 1978-01-19 | 1983-03-24 | E. Sachs & Co. Ltd | Fascia gutter |
US4411107A (en) * | 1980-02-01 | 1983-10-25 | Disco Co., Ltd. | Grinding wheel for flat plates |
FR2505713A1 (fr) * | 1981-05-18 | 1982-11-19 | Procedes Equip Sciences Ind Sa | Porte-plaquette pour machines a polir des plaquettes minces, fragiles et deformables |
DE3148957C2 (de) * | 1981-12-10 | 1987-01-02 | Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen | Verfahren zum Herstellen rückseitig oberflächengestörter Halbleiterscheiben |
JPS58184727A (ja) * | 1982-04-23 | 1983-10-28 | Disco Abrasive Sys Ltd | シリコンウェ−ハの面を研削する方法 |
JPS62243332A (ja) * | 1986-04-15 | 1987-10-23 | Toshiba Corp | 半導体ウエハの加工方法 |
DE3771857D1 (de) * | 1986-12-08 | 1991-09-05 | Sumitomo Electric Industries | Flaechenschleifmaschine. |
JPS6437025A (en) * | 1987-08-03 | 1989-02-07 | Sumitomo Electric Industries | Manufacture of semiconductor device |
-
1990
- 1990-09-05 JP JP2235152A patent/JP2610703B2/ja not_active Expired - Lifetime
-
1991
- 1991-08-20 KR KR1019910014294A patent/KR940002915B1/ko not_active IP Right Cessation
- 1991-09-03 AU AU83538/91A patent/AU649063B2/en not_active Ceased
- 1991-09-04 DK DK91114907.8T patent/DK0475259T3/da active
- 1991-09-04 US US07/754,906 patent/US5122481A/en not_active Expired - Lifetime
- 1991-09-04 CA CA002050675A patent/CA2050675A1/en not_active Abandoned
- 1991-09-04 EP EP91114907A patent/EP0475259B1/en not_active Expired - Lifetime
- 1991-09-04 DE DE69112545T patent/DE69112545T2/de not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023132518A1 (ko) * | 2022-01-10 | 2023-07-13 | 도레이첨단소재 주식회사 | 고강도 메타 아라미드 섬유 및 그의 제조방법 |
KR20240017874A (ko) * | 2022-01-10 | 2024-02-08 | 도레이첨단소재 주식회사 | 고강도 메타 아라미드 섬유 및 그의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
EP0475259A2 (en) | 1992-03-18 |
KR940002915B1 (ko) | 1994-04-07 |
JPH04115528A (ja) | 1992-04-16 |
DE69112545D1 (de) | 1995-10-05 |
US5122481A (en) | 1992-06-16 |
EP0475259A3 (en) | 1992-12-16 |
DK0475259T3 (da) | 1996-01-15 |
JP2610703B2 (ja) | 1997-05-14 |
EP0475259B1 (en) | 1995-08-30 |
CA2050675A1 (en) | 1992-03-06 |
DE69112545T2 (de) | 1996-05-02 |
AU649063B2 (en) | 1994-05-12 |
AU8353891A (en) | 1992-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR920007104A (ko) | 반도체소자의 제조방법 | |
EP0362838A3 (en) | A method of fabricating semiconductor devices | |
KR960009043A (ko) | 질화 규소의 에칭 방법 | |
KR960017938A (ko) | 에피텍셜 웨이퍼와 그의 제조방법 | |
KR890007364A (ko) | 반도체 소자 제조 방법 | |
KR920003408A (ko) | 반도체 기판의 제조 방법 | |
KR970023756A (ko) | 반도체장치의 스페이서 형성방법 | |
KR970003812A (ko) | 반도체 소자의 분리방법 | |
KR960039324A (ko) | 알파입자에 의한 소프트에러율을 감소시키기 위한 반도체 메모리장치 및 이의 제조방법 | |
KR950021186A (ko) | 웨이퍼 오염방지 방법 | |
KR970053478A (ko) | 반도체 장치의 소자 분리 방법 | |
KR960026127A (ko) | 고집적 반도체 소자의 리세스 어레이 형성 방법 | |
KR940027186A (ko) | 반도체 소자의 필드산화막 제조방법 | |
KR890015371A (ko) | 반도체 제조방법 | |
KR970053419A (ko) | 반도체장치의 제조방법 | |
KR920001678A (ko) | 금속 배선의 알루미늄 산화막 형성 제조방법 | |
KR960019538A (ko) | 두께를 초과하여 형성된 층의 식각방법 | |
KR970051889A (ko) | 반도체 소자의 자기 정렬 마스크 형성방법 | |
KR960039244A (ko) | 불순물 침투 공정용 테스트 웨이퍼의 재생방법 | |
KR920003546A (ko) | 반도체 제조방법 | |
KR970052785A (ko) | 반도체 소자 제조방법 | |
KR930017139A (ko) | 반도체 장치의 제조방법 | |
KR890002993A (ko) | 반도체장치의 제조방법 | |
KR900002432A (ko) | 반도체의 사이드벽 형성방법 | |
KR970053117A (ko) | 반도체소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20040323 Year of fee payment: 11 |
|
LAPS | Lapse due to unpaid annual fee |