DE69032571D1 - Verfahren zur Herstellung von Halbleiteranordnungen mit durch Graben isolierten Komponenten - Google Patents

Verfahren zur Herstellung von Halbleiteranordnungen mit durch Graben isolierten Komponenten

Info

Publication number
DE69032571D1
DE69032571D1 DE69032571T DE69032571T DE69032571D1 DE 69032571 D1 DE69032571 D1 DE 69032571D1 DE 69032571 T DE69032571 T DE 69032571T DE 69032571 T DE69032571 T DE 69032571T DE 69032571 D1 DE69032571 D1 DE 69032571D1
Authority
DE
Germany
Prior art keywords
trench
semiconductor devices
manufacturing semiconductor
isolated components
isolated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032571T
Other languages
English (en)
Other versions
DE69032571T2 (de
Inventor
Naoto Miyashita
Koichi Takahashi
Hironori Sonobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69032571D1 publication Critical patent/DE69032571D1/de
Publication of DE69032571T2 publication Critical patent/DE69032571T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE69032571T 1989-06-14 1990-06-13 Verfahren zur Herstellung von Halbleiteranordnungen mit durch Graben isolierten Komponenten Expired - Fee Related DE69032571T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15154289 1989-06-14

Publications (2)

Publication Number Publication Date
DE69032571D1 true DE69032571D1 (de) 1998-09-24
DE69032571T2 DE69032571T2 (de) 1999-02-04

Family

ID=15520790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032571T Expired - Fee Related DE69032571T2 (de) 1989-06-14 1990-06-13 Verfahren zur Herstellung von Halbleiteranordnungen mit durch Graben isolierten Komponenten

Country Status (4)

Country Link
EP (1) EP0402897B1 (de)
JP (1) JP2839651B2 (de)
KR (1) KR930006594B1 (de)
DE (1) DE69032571T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736419B2 (ja) * 1990-02-09 1995-04-19 株式会社東芝 半導体装置及びその製造方法
JPH05152429A (ja) * 1991-11-28 1993-06-18 Nec Corp 半導体装置の製造方法
JP4657614B2 (ja) * 2004-03-09 2011-03-23 Ｏｋｉセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
JP5292984B2 (ja) * 2008-08-08 2013-09-18 株式会社デンソー 半導体装置の製造方法
JP5691074B2 (ja) 2008-08-20 2015-04-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472873A (en) * 1981-10-22 1984-09-25 Fairchild Camera And Instrument Corporation Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
US4486266A (en) * 1983-08-12 1984-12-04 Tektronix, Inc. Integrated circuit method
JPS60136327A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置の製造方法
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate

Also Published As

Publication number Publication date
EP0402897A3 (de) 1993-12-15
KR930006594B1 (ko) 1993-07-21
JP2839651B2 (ja) 1998-12-16
DE69032571T2 (de) 1999-02-04
EP0402897B1 (de) 1998-08-19
JPH03183152A (ja) 1991-08-09
KR910001938A (ko) 1991-01-31
EP0402897A2 (de) 1990-12-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee