DE69429978T2 - Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen - Google Patents

Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen

Info

Publication number
DE69429978T2
DE69429978T2 DE69429978T DE69429978T DE69429978T2 DE 69429978 T2 DE69429978 T2 DE 69429978T2 DE 69429978 T DE69429978 T DE 69429978T DE 69429978 T DE69429978 T DE 69429978T DE 69429978 T2 DE69429978 T2 DE 69429978T2
Authority
DE
Germany
Prior art keywords
production
semiconductor devices
isolation zones
zones
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69429978T
Other languages
English (en)
Other versions
DE69429978D1 (de
Inventor
Fumitomo Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69429978D1 publication Critical patent/DE69429978D1/de
Publication of DE69429978T2 publication Critical patent/DE69429978T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE69429978T 1993-12-27 1994-12-27 Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen Expired - Lifetime DE69429978T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5333195A JPH07193121A (ja) 1993-12-27 1993-12-27 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69429978D1 DE69429978D1 (de) 2002-04-04
DE69429978T2 true DE69429978T2 (de) 2002-10-02

Family

ID=18263378

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69429978T Expired - Lifetime DE69429978T2 (de) 1993-12-27 1994-12-27 Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen

Country Status (5)

Country Link
US (1) US5766823A (de)
EP (1) EP0660389B1 (de)
JP (1) JPH07193121A (de)
KR (1) KR0179681B1 (de)
DE (1) DE69429978T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3688816B2 (ja) * 1996-07-16 2005-08-31 株式会社東芝 半導体装置の製造方法
US6114741A (en) * 1996-12-13 2000-09-05 Texas Instruments Incorporated Trench isolation of a CMOS structure
KR19980051524A (ko) * 1996-12-23 1998-09-15 김영환 반도체소자의 소자분리막 제조방법
KR19980060506A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 소자 분리막 형성방법
JP3614267B2 (ja) * 1997-02-05 2005-01-26 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JPH10223747A (ja) * 1997-02-06 1998-08-21 Nec Corp 半導体装置の製造方法
JP3904676B2 (ja) 1997-04-11 2007-04-11 株式会社ルネサステクノロジ トレンチ型素子分離構造の製造方法およびトレンチ型素子分離構造
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
US5981356A (en) * 1997-07-28 1999-11-09 Integrated Device Technology, Inc. Isolation trenches with protected corners
US5837612A (en) * 1997-08-01 1998-11-17 Motorola, Inc. Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation
US6103635A (en) * 1997-10-28 2000-08-15 Fairchild Semiconductor Corp. Trench forming process and integrated circuit device including a trench
US6054343A (en) * 1998-01-26 2000-04-25 Texas Instruments Incorporated Nitride trench fill process for increasing shallow trench isolation (STI) robustness
US5976948A (en) * 1998-02-19 1999-11-02 Advanced Micro Devices Process for forming an isolation region with trench cap
US6214699B1 (en) * 1998-04-01 2001-04-10 Texas Instruments Incorporated Method for forming an isolation structure in a substrate
KR19990079343A (ko) * 1998-04-03 1999-11-05 윤종용 반도체장치의 트렌치 소자분리 방법
US6265282B1 (en) * 1998-08-17 2001-07-24 Micron Technology, Inc. Process for making an isolation structure
JP3540633B2 (ja) * 1998-11-11 2004-07-07 株式会社東芝 半導体装置の製造方法
FR2792113B1 (fr) * 1999-04-06 2002-08-09 St Microelectronics Sa Procede de realisation d'un circuit integre comportant une tranchee d'isolation laterale accolee a une zone active d'un transistor, et circuit integre correspondant
KR20000066999A (ko) * 1999-04-22 2000-11-15 김영환 반도체 장치의 분리구조 제조방법
JP2001118920A (ja) * 1999-10-15 2001-04-27 Seiko Epson Corp 半導体装置およびその製造方法
US6406982B2 (en) * 2000-06-05 2002-06-18 Denso Corporation Method of improving epitaxially-filled trench by smoothing trench prior to filling
JP2002203894A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 半導体装置の製造方法
KR100546852B1 (ko) * 2002-12-28 2006-01-25 동부아남반도체 주식회사 반도체 소자의 제조 방법
US7119403B2 (en) * 2003-10-16 2006-10-10 International Business Machines Corporation High performance strained CMOS devices
US6905943B2 (en) * 2003-11-06 2005-06-14 Texas Instruments Incorporated Forming a trench to define one or more isolation regions in a semiconductor structure

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048175B1 (de) * 1980-09-17 1986-04-23 Hitachi, Ltd. Halbleiterbauelement und Verfahren zu dessen Herstellung
CA1204525A (en) * 1982-11-29 1986-05-13 Tetsu Fukano Method for forming an isolation region for electrically isolating elements
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JP2666384B2 (ja) * 1988-06-30 1997-10-22 ソニー株式会社 半導体装置の製造方法
US5290664A (en) * 1990-03-29 1994-03-01 Sharp Kabushiki Kaisha Method for preparing electrode for semiconductor device
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
JPH0629239A (ja) * 1992-02-27 1994-02-04 Eastman Kodak Co リフト−オフプロセスを利用した半導体素子におけるセルフアライン拡散バリアの製造方法及び拡散バリアを有する半導体素子

Also Published As

Publication number Publication date
EP0660389B1 (de) 2002-02-27
JPH07193121A (ja) 1995-07-28
KR0179681B1 (ko) 1999-04-15
US5766823A (en) 1998-06-16
DE69429978D1 (de) 2002-04-04
EP0660389A2 (de) 1995-06-28
EP0660389A3 (de) 1997-12-29

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Legal Events

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8364 No opposition during term of opposition