DE69434536D1 - Verfahren zur Herstellung von halbleitenden Wafern - Google Patents

Verfahren zur Herstellung von halbleitenden Wafern

Info

Publication number
DE69434536D1
DE69434536D1 DE69434536T DE69434536T DE69434536D1 DE 69434536 D1 DE69434536 D1 DE 69434536D1 DE 69434536 T DE69434536 T DE 69434536T DE 69434536 T DE69434536 T DE 69434536T DE 69434536 D1 DE69434536 D1 DE 69434536D1
Authority
DE
Germany
Prior art keywords
production
semiconducting wafers
semiconducting
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69434536T
Other languages
English (en)
Other versions
DE69434536T2 (de
Inventor
Tadahiro Kato
Masami Nakano
Sunao Shima
Hisashi Masumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69434536D1 publication Critical patent/DE69434536D1/de
Application granted granted Critical
Publication of DE69434536T2 publication Critical patent/DE69434536T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
DE69434536T 1993-06-08 1994-06-01 Verfahren zur Herstellung von halbleitenden Wafern Expired - Lifetime DE69434536T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13776393 1993-06-08
JP5137763A JP2910507B2 (ja) 1993-06-08 1993-06-08 半導体ウエーハの製造方法

Publications (2)

Publication Number Publication Date
DE69434536D1 true DE69434536D1 (de) 2005-12-15
DE69434536T2 DE69434536T2 (de) 2006-08-10

Family

ID=15206266

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69434536T Expired - Lifetime DE69434536T2 (de) 1993-06-08 1994-06-01 Verfahren zur Herstellung von halbleitenden Wafern

Country Status (4)

Country Link
US (1) US5494862A (de)
EP (1) EP0628992B1 (de)
JP (1) JP2910507B2 (de)
DE (1) DE69434536T2 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718873A3 (de) * 1994-12-21 1998-04-15 MEMC Electronic Materials, Inc. Reinigungsverfahren für hydrophobe Siliziumscheiben
US5899743A (en) * 1995-03-13 1999-05-04 Komatsu Electronic Metals Co., Ltd. Method for fabricating semiconductor wafers
JP3828176B2 (ja) * 1995-02-28 2006-10-04 コマツ電子金属株式会社 半導体ウェハの製造方法
JP3134719B2 (ja) * 1995-06-23 2001-02-13 信越半導体株式会社 半導体ウェーハ研磨用研磨剤及び研磨方法
US5968849A (en) * 1995-06-26 1999-10-19 Motorola, Inc. Method for pre-shaping a semiconductor substrate for polishing and structure
TW308561B (de) * 1995-08-24 1997-06-21 Mutsubishi Gum Kk
US5950643A (en) * 1995-09-06 1999-09-14 Miyazaki; Takeshiro Wafer processing system
US5807766A (en) * 1995-09-21 1998-09-15 Mcbride; Donald G. Process for attaching a silicon chip to a circuit board using a block of encapsulated wires and the block of wires manufactured by the process
JP3534213B2 (ja) * 1995-09-30 2004-06-07 コマツ電子金属株式会社 半導体ウェハの製造方法
US5855735A (en) * 1995-10-03 1999-01-05 Kobe Precision, Inc. Process for recovering substrates
JP3317330B2 (ja) * 1995-12-27 2002-08-26 信越半導体株式会社 半導体鏡面ウェーハの製造方法
JPH09270401A (ja) * 1996-01-31 1997-10-14 Shin Etsu Handotai Co Ltd 半導体ウェーハの研磨方法
JP3620554B2 (ja) * 1996-03-25 2005-02-16 信越半導体株式会社 半導体ウェーハ製造方法
US5792566A (en) * 1996-07-02 1998-08-11 American Xtal Technology Single crystal wafers
JPH10135165A (ja) * 1996-10-29 1998-05-22 Komatsu Electron Metals Co Ltd 半導体ウェハの製法
DE19647635A1 (de) * 1996-11-18 1998-05-20 Wacker Siltronic Halbleitermat Verfahren und Vorrichtung zum Entfernen einer Halbleiterscheibe von einer ebenen Unterlage
US5821166A (en) * 1996-12-12 1998-10-13 Komatsu Electronic Metals Co., Ltd. Method of manufacturing semiconductor wafers
JP3620683B2 (ja) * 1996-12-27 2005-02-16 信越半導体株式会社 半導体ウエーハの製造方法
JP3305610B2 (ja) * 1997-02-21 2002-07-24 信越半導体株式会社 ラッピング後の半導体ウエーハの洗浄方法
EP1019955A1 (de) * 1997-08-21 2000-07-19 MEMC Electronic Materials, Inc. Verfahren zur verarbeitung von halbleiterwafern
JPH11135474A (ja) 1997-10-30 1999-05-21 Komatsu Electron Metals Co Ltd 半導体鏡面ウェハおよびその製造方法
MY119304A (en) * 1997-12-11 2005-04-30 Shinetsu Handotai Kk Silicon wafer etching method and silicon wafer etchant
JPH11254314A (ja) * 1998-03-10 1999-09-21 Speedfam Co Ltd ワーク面加工装置
JP3271658B2 (ja) * 1998-03-23 2002-04-02 信越半導体株式会社 半導体シリコン単結晶ウェーハのラップ又は研磨方法
DE19833257C1 (de) * 1998-07-23 1999-09-30 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe
US5922135A (en) * 1998-09-04 1999-07-13 Seh America, Inc. Method of removing residual wax from silicon wafer polishing plate
JP3664593B2 (ja) * 1998-11-06 2005-06-29 信越半導体株式会社 半導体ウエーハおよびその製造方法
US6214704B1 (en) 1998-12-16 2001-04-10 Memc Electronic Materials, Inc. Method of processing semiconductor wafers to build in back surface damage
EP1134808B1 (de) 1999-07-15 2011-10-05 Shin-Etsu Handotai Co., Ltd. Herstellungsverfahren einer verbundscheibe
DE19953152C1 (de) * 1999-11-04 2001-02-15 Wacker Siltronic Halbleitermat Verfahren zur naßchemischen Oberflächenbehandlung einer Halbleiterscheibe
WO2001034877A1 (en) * 1999-11-10 2001-05-17 Memc Electronic Materials, Inc. Alkaline etching solution and process for etching semiconductor wafers
AU2001247500A1 (en) * 2000-03-17 2001-10-03 Wafer Solutions, Inc. Systems and methods to reduce grinding marks and metallic contamination
JP4846915B2 (ja) * 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
WO2002001616A1 (fr) * 2000-06-29 2002-01-03 Shin-Etsu Handotai Co., Ltd. Procede de traitement d'une plaquette de semi-conducteur et plaquette de semi-conducteur
KR20030024834A (ko) * 2000-08-07 2003-03-26 엠이엠씨 일렉트로닉 머티리얼즈 인코포레이티드 양측 폴리싱을 이용한 반도체 웨이퍼 처리 방법
KR100832942B1 (ko) * 2000-10-26 2008-05-27 신에츠 한도타이 가부시키가이샤 웨이퍼의 제조방법 및 연마장치 및 웨이퍼
US6672943B2 (en) 2001-01-26 2004-01-06 Wafer Solutions, Inc. Eccentric abrasive wheel for wafer processing
US6632012B2 (en) 2001-03-30 2003-10-14 Wafer Solutions, Inc. Mixing manifold for multiple inlet chemistry fluids
US7416962B2 (en) * 2002-08-30 2008-08-26 Siltronic Corporation Method for processing a semiconductor wafer including back side grinding
JP2005039155A (ja) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及びそれに用いる半導体基板の製造方法
JP2005203507A (ja) * 2004-01-14 2005-07-28 Siltronic Japan Corp 半導体ウェーハの加工方法および半導体ウェーハ処理装置
JP5045008B2 (ja) * 2005-07-08 2012-10-10 株式会社ニコン 液浸露光用基板、露光方法及びデバイス製造方法
WO2007007723A1 (ja) * 2005-07-08 2007-01-18 Nikon Corporation 液浸露光用基板、露光方法及びデバイス製造方法
DE102006022089A1 (de) * 2006-05-11 2007-11-15 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe mit einr profilierten Kante
US20080206992A1 (en) * 2006-12-29 2008-08-28 Siltron Inc. Method for manufacturing high flatness silicon wafer
US9281251B2 (en) * 2013-08-09 2016-03-08 Tokyo Electron Limited Substrate backside texturing
US9455211B2 (en) 2013-09-11 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with openings in buffer layer
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
WO2017034533A1 (en) * 2015-08-22 2017-03-02 Tokyo Electron Limited Substrate backside texturing
CN112053936B (zh) * 2020-09-22 2024-06-11 粤芯半导体技术股份有限公司 晶圆背面粗糙化控制方法以及功率器件制造方法

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JPS54110783A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Semiconductor substrate and its manufacture
JPS56169346A (en) * 1980-05-30 1981-12-26 Hitachi Ltd Manufacture of semiconductor device
US4343662A (en) * 1981-03-31 1982-08-10 Atlantic Richfield Company Manufacturing semiconductor wafer devices by simultaneous slicing and etching
JPS5958827A (ja) * 1982-09-28 1984-04-04 Toshiba Corp 半導体ウエ−ハ、半導体ウエ−ハの製造方法及び半導体ウエ−ハの製造装置
DE3246480A1 (de) * 1982-12-15 1984-06-20 Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen Verfahren zur herstellung von halbleiterscheiben mit getternder scheibenrueckseite
JPS61182233A (ja) * 1985-02-08 1986-08-14 Hitachi Ltd ウエハおよびその製造方法
JPS6482814A (en) * 1987-09-25 1989-03-28 Shinetsu Chemical Co Piezoelectric body monocrystal wafer and its manufacture
JPH0753640B2 (ja) * 1988-10-05 1995-06-07 住友電気工業株式会社 ＧａＡｓ単結晶鏡面ウエハおよびその製造方法
JPH02222144A (ja) * 1989-02-23 1990-09-04 Nkk Corp 半導体ウエーハ及びその製造方法
JP2541680B2 (ja) * 1990-03-30 1996-10-09 直江津電子工業株式会社 ディスクリ―ト素子用シリコン基板
EP0460437B1 (de) * 1990-05-18 1997-09-10 Fujitsu Limited Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates
US5320706A (en) * 1991-10-15 1994-06-14 Texas Instruments Incorporated Removing slurry residue from semiconductor wafer planarization
JP2839801B2 (ja) * 1992-09-18 1998-12-16 三菱マテリアル株式会社 ウェーハの製造方法

Also Published As

Publication number Publication date
EP0628992A2 (de) 1994-12-14
EP0628992B1 (de) 2005-11-09
US5494862A (en) 1996-02-27
DE69434536T2 (de) 2006-08-10
JP2910507B2 (ja) 1999-06-23
JPH06349795A (ja) 1994-12-22
EP0628992A3 (de) 1997-05-02

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Legal Events

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