DE69132118T2 - Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen - Google Patents

Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen

Info

Publication number
DE69132118T2
DE69132118T2 DE69132118T DE69132118T DE69132118T2 DE 69132118 T2 DE69132118 T2 DE 69132118T2 DE 69132118 T DE69132118 T DE 69132118T DE 69132118 T DE69132118 T DE 69132118T DE 69132118 T2 DE69132118 T2 DE 69132118T2
Authority
DE
Germany
Prior art keywords
production
semiconductor devices
isolation zones
zones
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69132118T
Other languages
English (en)
Other versions
DE69132118D1 (de
Inventor
Katsuji Iguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69132118D1 publication Critical patent/DE69132118D1/de
Application granted granted Critical
Publication of DE69132118T2 publication Critical patent/DE69132118T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
DE69132118T 1990-02-23 1991-02-22 Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen Expired - Lifetime DE69132118T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2043393A JP2597022B2 (ja) 1990-02-23 1990-02-23 素子分離領域の形成方法

Publications (2)

Publication Number Publication Date
DE69132118D1 DE69132118D1 (de) 2000-05-25
DE69132118T2 true DE69132118T2 (de) 2000-09-28

Family

ID=12662547

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132118T Expired - Lifetime DE69132118T2 (de) 1990-02-23 1991-02-22 Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen

Country Status (5)

Country Link
US (1) US5116779A (de)
EP (1) EP0444836B1 (de)
JP (1) JP2597022B2 (de)
KR (1) KR950000102B1 (de)
DE (1) DE69132118T2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399516A (en) * 1992-03-12 1995-03-21 International Business Machines Corporation Method of making shadow RAM cell having a shallow trench EEPROM
EP0631306B1 (de) * 1993-06-23 2000-04-26 Siemens Aktiengesellschaft Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
EP0631305B1 (de) * 1993-06-23 1998-04-15 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Isolationsgrabens in einem Substrat für Smart-Power-Technologien
EP0635884A1 (de) * 1993-07-13 1995-01-25 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Grabens in einem Substrat und dessen Verwendung in der Smart-Power-Technologie
DE69434736D1 (de) * 1993-08-31 2006-06-22 St Microelectronics Inc Isolationsstruktur und Verfahren zur Herstellung
JP3022714B2 (ja) * 1993-10-29 2000-03-21 日本電気株式会社 半導体装置およびその製造方法
US5438016A (en) * 1994-03-02 1995-08-01 Micron Semiconductor, Inc. Method of semiconductor device isolation employing polysilicon layer for field oxide formation
US5478758A (en) * 1994-06-03 1995-12-26 At&T Corp. Method of making a getterer for multi-layer wafers
TW274628B (de) * 1994-06-03 1996-04-21 At & T Corp
US5455194A (en) * 1995-03-06 1995-10-03 Motorola Inc. Encapsulation method for localized oxidation of silicon with trench isolation
KR0147630B1 (ko) * 1995-04-21 1998-11-02 김광호 반도체 장치의 소자분리방법
KR100361761B1 (ko) * 1995-06-02 2003-02-05 주식회사 하이닉스반도체 반도체소자의소자분리절연막형성방법
KR100214068B1 (ko) * 1995-11-21 1999-08-02 김영환 반도체 장치의 소자분리막 형성방법
US5933746A (en) * 1996-04-23 1999-08-03 Harris Corporation Process of forming trench isolation device
JPH10209269A (ja) * 1997-01-09 1998-08-07 Texas Instr Inc <Ti> トレンチと選択酸化を組み合わせるための分離方法
US6037239A (en) * 1997-04-23 2000-03-14 Elantec, Inc. Method for making a contact structure for a polysilicon filled trench isolation
US6057209A (en) * 1997-07-10 2000-05-02 Advanced Micro Devices, Inc. Semiconductor device having a nitrogen bearing isolation region
US6136664A (en) * 1997-08-07 2000-10-24 International Business Machines Corporation Filling of high aspect ratio trench isolation
US5976950A (en) * 1997-11-13 1999-11-02 National Semiconductor Corporation Polysilicon coated swami (sidewall masked isolation)
US6118167A (en) * 1997-11-13 2000-09-12 National Semiconductor Corporation Polysilicon coated nitride-lined shallow trench
KR100253406B1 (ko) 1998-01-20 2000-04-15 김영환 반도체 파워 집적회로에서의 소자격리구조 및 그 방법
US5989977A (en) * 1998-04-20 1999-11-23 Texas Instruments - Acer Incorporated Shallow trench isolation process
US6037018A (en) * 1998-07-01 2000-03-14 Taiwan Semiconductor Maufacturing Company Shallow trench isolation filled by high density plasma chemical vapor deposition
TW400605B (en) * 1999-01-16 2000-08-01 United Microelectronics Corp The manufacturing method of the Shallow Trench Isolation (STI)
US6500729B1 (en) 2000-06-02 2002-12-31 Agere Systems Guardian Corp. Method for reducing dishing related issues during the formation of shallow trench isolation structures
US6573154B1 (en) * 2000-10-26 2003-06-03 Institute Of Microelectronics High aspect ratio trench isolation process for surface micromachined sensors and actuators
DE10234165B4 (de) * 2002-07-26 2008-01-03 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Füllen eines Grabens, der in einem Substrat gebildet ist, mit einem isolierenden Material
US6933206B2 (en) * 2003-10-10 2005-08-23 Infineon Technologies Ag Trench isolation employing a high aspect ratio trench
JP4657614B2 (ja) * 2004-03-09 2011-03-23 Ｏｋｉセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
US7776708B1 (en) * 2005-08-11 2010-08-17 National Semiconductor Corporation System and method for providing a nitride cap over a polysilicon filled trench to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device
US7863153B1 (en) 2006-07-13 2011-01-04 National Semiconductor Corporation System and method for creating different field oxide profiles in a locos process

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58175843A (ja) * 1982-04-08 1983-10-15 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法
JPS59135743A (ja) * 1983-01-24 1984-08-04 Hitachi Ltd 半導体装置およびその製造方法
JPS59227136A (ja) * 1983-06-08 1984-12-20 Matsushita Electronics Corp 半導体装置の製造方法
JPS6054453A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体集積回路装置の製造方法
US4666557A (en) * 1984-12-10 1987-05-19 Ncr Corporation Method for forming channel stops in vertical semiconductor surfaces
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
GB2200794A (en) * 1986-11-19 1988-08-10 Plessey Co Plc Semiconductor device manufacture
JP2590867B2 (ja) * 1987-03-27 1997-03-12 ソニー株式会社 メモリ装置の製造方法
JPS63314844A (ja) * 1987-06-18 1988-12-22 Toshiba Corp 半導体装置の製造方法
JPS6445165A (en) * 1987-08-13 1989-02-17 Toshiba Corp Semiconductor device and manufacture thereof
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate

Also Published As

Publication number Publication date
DE69132118D1 (de) 2000-05-25
JP2597022B2 (ja) 1997-04-02
JPH03245553A (ja) 1991-11-01
EP0444836A2 (de) 1991-09-04
KR950000102B1 (ko) 1995-01-09
US5116779A (en) 1992-05-26
EP0444836A3 (en) 1991-11-06
EP0444836B1 (de) 2000-04-19

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