DE69232827D1 - Verfahren zur Herstellung aktiver Zonen mit planarer Isolation - Google Patents

Verfahren zur Herstellung aktiver Zonen mit planarer Isolation

Info

Publication number
DE69232827D1
DE69232827D1 DE69232827T DE69232827T DE69232827D1 DE 69232827 D1 DE69232827 D1 DE 69232827D1 DE 69232827 T DE69232827 T DE 69232827T DE 69232827 T DE69232827 T DE 69232827T DE 69232827 D1 DE69232827 D1 DE 69232827D1
Authority
DE
Germany
Prior art keywords
production
active zones
planar isolation
isolation
planar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69232827T
Other languages
English (en)
Other versions
DE69232827T2 (de
Inventor
Robert Otis Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69232827D1 publication Critical patent/DE69232827D1/de
Application granted granted Critical
Publication of DE69232827T2 publication Critical patent/DE69232827T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69232827T 1991-03-28 1992-03-27 Verfahren zur Herstellung aktiver Zonen mit planarer Isolation Expired - Fee Related DE69232827T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/677,649 US5135884A (en) 1991-03-28 1991-03-28 Method of producing isoplanar isolated active regions

Publications (2)

Publication Number Publication Date
DE69232827D1 true DE69232827D1 (de) 2002-11-28
DE69232827T2 DE69232827T2 (de) 2003-03-27

Family

ID=24719591

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232827T Expired - Fee Related DE69232827T2 (de) 1991-03-28 1992-03-27 Verfahren zur Herstellung aktiver Zonen mit planarer Isolation

Country Status (5)

Country Link
US (2) US5135884A (de)
EP (1) EP0506473B1 (de)
JP (1) JPH05102292A (de)
KR (1) KR920018873A (de)
DE (1) DE69232827T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453396A (en) * 1994-05-31 1995-09-26 Micron Technology, Inc. Sub-micron diffusion area isolation with SI-SEG for a DRAM array
JP2686735B2 (ja) * 1994-12-30 1997-12-08 現代電子産業株式会社 半導体装置の素子分離方法
US5818098A (en) * 1996-02-29 1998-10-06 Motorola, Inc. Semiconductor device having a pedestal
CN1495915A (zh) * 1998-07-03 2004-05-12 ������������ʽ���� 光电转换元件
US6084269A (en) * 1998-12-21 2000-07-04 Motorola, Inc. Semiconductor device and method of making
US6118171A (en) * 1998-12-21 2000-09-12 Motorola, Inc. Semiconductor device having a pedestal structure and method of making
US7011673B2 (en) 1999-11-22 2006-03-14 Fischell Robert E Stent delivery system with a fixed guide wire
TW556311B (en) * 2001-07-31 2003-10-01 Infineon Technologies Ag Method for filling trenches in integrated semiconductor circuits
US10256093B2 (en) * 2015-11-30 2019-04-09 Alliance For Sustainable Energy, Llc Selective area growth of semiconductors using patterned sol-gel materials

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3861968A (en) * 1972-06-19 1975-01-21 Ibm Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
US3883948A (en) * 1974-01-02 1975-05-20 Signetics Corp Semiconductor structure and method
US3969749A (en) * 1974-04-01 1976-07-13 Texas Instruments Incorporated Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide
JPS53144690A (en) * 1977-05-23 1978-12-16 Nippon Telegr & Teleph Corp <Ntt> Production of semiconductor device
JPS5423388A (en) * 1977-07-22 1979-02-21 Hitachi Ltd Semiconductor integrated-circuit device and its manufacture
JPS55134946A (en) * 1979-04-09 1980-10-21 Nec Corp Manufacturing of semiconductor device
US4677456A (en) * 1979-05-25 1987-06-30 Raytheon Company Semiconductor structure and manufacturing method
DE3129558A1 (de) * 1980-07-28 1982-03-18 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Verfahren zur herstellung einer integrierten halbleiterschaltung
JPS5756942A (en) * 1980-09-19 1982-04-05 Tadatsugu Ito Manufacture of silicon semiconductor device
DE3265339D1 (en) * 1981-03-20 1985-09-19 Toshiba Kk Method for manufacturing semiconductor device
JPS5823431A (ja) * 1981-08-04 1983-02-12 Mitsubishi Electric Corp 半導体基体の製作方法
US4400411A (en) * 1982-07-19 1983-08-23 The United States Of America As Represented By The Secretary Of The Air Force Technique of silicon epitaxial refill
JPS59134819A (ja) * 1982-09-03 1984-08-02 Nec Corp 半導体基板の製造方法
FR2571544B1 (fr) * 1984-10-05 1987-07-31 Haond Michel Procede de fabrication d'ilots de silicium monocristallin isoles electriquement les uns des autres
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
JPS61170018A (ja) * 1985-01-23 1986-07-31 Mitsubishi Electric Corp エピタキシヤル成長法による半導体の製造方法
JPS61203632A (ja) * 1985-03-06 1986-09-09 Nec Corp 半導体基板
WO1987001239A1 (en) * 1985-08-15 1987-02-26 Ncr Corporation Dielectric isolation structure for integrated circuits
US4728624A (en) * 1985-10-31 1988-03-01 International Business Machines Corporation Selective epitaxial growth structure and isolation
US4810667A (en) * 1987-04-28 1989-03-07 Texas Instruments Incorporated Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer
JPS6410644A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Manufacture of semiconductor device
US5049968A (en) * 1988-02-08 1991-09-17 Kabushiki Kaisha Toshiba Dielectrically isolated substrate and semiconductor device using the same
US4975759A (en) * 1989-03-06 1990-12-04 Delco Electronics Corporation Semiconductive stalk structure

Also Published As

Publication number Publication date
EP0506473B1 (de) 2002-10-23
US5135884A (en) 1992-08-04
JPH05102292A (ja) 1993-04-23
EP0506473A2 (de) 1992-09-30
US5548154A (en) 1996-08-20
DE69232827T2 (de) 2003-03-27
KR920018873A (ko) 1992-10-22
EP0506473A3 (en) 1995-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee