JPH07193121A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JPH07193121A JPH07193121A JP5333195A JP33319593A JPH07193121A JP H07193121 A JPH07193121 A JP H07193121A JP 5333195 A JP5333195 A JP 5333195A JP 33319593 A JP33319593 A JP 33319593A JP H07193121 A JPH07193121 A JP H07193121A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- substrate
- etching
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 43
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000000945 filler Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 9
- 238000000926 separation method Methods 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 10
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 230000002950 deficient Effects 0.000 abstract 2
- 238000007670 refining Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5333195A JPH07193121A (ja) | 1993-12-27 | 1993-12-27 | 半導体装置の製造方法 |
KR1019940036760A KR0179681B1 (ko) | 1993-12-27 | 1994-12-26 | 반도체장치의 제조방법 |
EP94120685A EP0660389B1 (de) | 1993-12-27 | 1994-12-27 | Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen |
DE69429978T DE69429978T2 (de) | 1993-12-27 | 1994-12-27 | Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen |
US08/935,058 US5766823A (en) | 1993-12-27 | 1997-09-22 | Method of manufacturing semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5333195A JPH07193121A (ja) | 1993-12-27 | 1993-12-27 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07193121A true JPH07193121A (ja) | 1995-07-28 |
Family
ID=18263378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5333195A Pending JPH07193121A (ja) | 1993-12-27 | 1993-12-27 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5766823A (de) |
EP (1) | EP0660389B1 (de) |
JP (1) | JPH07193121A (de) |
KR (1) | KR0179681B1 (de) |
DE (1) | DE69429978T2 (de) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980051524A (ko) * | 1996-12-23 | 1998-09-15 | 김영환 | 반도체소자의 소자분리막 제조방법 |
KR19980060506A (ko) * | 1996-12-31 | 1998-10-07 | 김영환 | 반도체 소자의 소자 분리막 형성방법 |
US6043135A (en) * | 1997-02-06 | 2000-03-28 | Nec Corporation | Process of fabricating a semiconductor device having trench isolation allowing pattern image to be exactly transferred to photo-resist layer extending thereon |
KR20000066999A (ko) * | 1999-04-22 | 2000-11-15 | 김영환 | 반도체 장치의 분리구조 제조방법 |
JP2001118920A (ja) * | 1999-10-15 | 2001-04-27 | Seiko Epson Corp | 半導体装置およびその製造方法 |
KR100313695B1 (ko) * | 1998-11-11 | 2001-11-17 | 니시무로 타이죠 | 반도체 장치의 제조 방법 |
KR100427153B1 (ko) * | 2001-01-04 | 2004-04-14 | 료덴 세미컨덕터 시스템 엔지니어링 (주) | 반도체 장치의 제조 방법 |
JP2007509492A (ja) * | 2003-10-16 | 2007-04-12 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 高性能の歪みcmosデバイス |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3688816B2 (ja) * | 1996-07-16 | 2005-08-31 | 株式会社東芝 | 半導体装置の製造方法 |
US6114741A (en) * | 1996-12-13 | 2000-09-05 | Texas Instruments Incorporated | Trench isolation of a CMOS structure |
JP3614267B2 (ja) * | 1997-02-05 | 2005-01-26 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP3904676B2 (ja) | 1997-04-11 | 2007-04-11 | 株式会社ルネサステクノロジ | トレンチ型素子分離構造の製造方法およびトレンチ型素子分離構造 |
US5960297A (en) * | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
US5981356A (en) * | 1997-07-28 | 1999-11-09 | Integrated Device Technology, Inc. | Isolation trenches with protected corners |
US5837612A (en) * | 1997-08-01 | 1998-11-17 | Motorola, Inc. | Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation |
US6103635A (en) * | 1997-10-28 | 2000-08-15 | Fairchild Semiconductor Corp. | Trench forming process and integrated circuit device including a trench |
US6054343A (en) * | 1998-01-26 | 2000-04-25 | Texas Instruments Incorporated | Nitride trench fill process for increasing shallow trench isolation (STI) robustness |
US5976948A (en) * | 1998-02-19 | 1999-11-02 | Advanced Micro Devices | Process for forming an isolation region with trench cap |
US6214699B1 (en) * | 1998-04-01 | 2001-04-10 | Texas Instruments Incorporated | Method for forming an isolation structure in a substrate |
KR19990079343A (ko) * | 1998-04-03 | 1999-11-05 | 윤종용 | 반도체장치의 트렌치 소자분리 방법 |
US6265282B1 (en) * | 1998-08-17 | 2001-07-24 | Micron Technology, Inc. | Process for making an isolation structure |
FR2792113B1 (fr) * | 1999-04-06 | 2002-08-09 | St Microelectronics Sa | Procede de realisation d'un circuit integre comportant une tranchee d'isolation laterale accolee a une zone active d'un transistor, et circuit integre correspondant |
US6406982B2 (en) * | 2000-06-05 | 2002-06-18 | Denso Corporation | Method of improving epitaxially-filled trench by smoothing trench prior to filling |
KR100546852B1 (ko) * | 2002-12-28 | 2006-01-25 | 동부아남반도체 주식회사 | 반도체 소자의 제조 방법 |
US6905943B2 (en) * | 2003-11-06 | 2005-06-14 | Texas Instruments Incorporated | Forming a trench to define one or more isolation regions in a semiconductor structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3174468D1 (en) * | 1980-09-17 | 1986-05-28 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
CA1204525A (en) * | 1982-11-29 | 1986-05-13 | Tetsu Fukano | Method for forming an isolation region for electrically isolating elements |
US4666556A (en) * | 1986-05-12 | 1987-05-19 | International Business Machines Corporation | Trench sidewall isolation by polysilicon oxidation |
JP2666384B2 (ja) * | 1988-06-30 | 1997-10-22 | ソニー株式会社 | 半導体装置の製造方法 |
US5290664A (en) * | 1990-03-29 | 1994-03-01 | Sharp Kabushiki Kaisha | Method for preparing electrode for semiconductor device |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
JPH0629239A (ja) * | 1992-02-27 | 1994-02-04 | Eastman Kodak Co | リフト−オフプロセスを利用した半導体素子におけるセルフアライン拡散バリアの製造方法及び拡散バリアを有する半導体素子 |
-
1993
- 1993-12-27 JP JP5333195A patent/JPH07193121A/ja active Pending
-
1994
- 1994-12-26 KR KR1019940036760A patent/KR0179681B1/ko not_active IP Right Cessation
- 1994-12-27 EP EP94120685A patent/EP0660389B1/de not_active Expired - Lifetime
- 1994-12-27 DE DE69429978T patent/DE69429978T2/de not_active Expired - Lifetime
-
1997
- 1997-09-22 US US08/935,058 patent/US5766823A/en not_active Expired - Lifetime
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980051524A (ko) * | 1996-12-23 | 1998-09-15 | 김영환 | 반도체소자의 소자분리막 제조방법 |
KR19980060506A (ko) * | 1996-12-31 | 1998-10-07 | 김영환 | 반도체 소자의 소자 분리막 형성방법 |
US6043135A (en) * | 1997-02-06 | 2000-03-28 | Nec Corporation | Process of fabricating a semiconductor device having trench isolation allowing pattern image to be exactly transferred to photo-resist layer extending thereon |
KR100313695B1 (ko) * | 1998-11-11 | 2001-11-17 | 니시무로 타이죠 | 반도체 장치의 제조 방법 |
KR20000066999A (ko) * | 1999-04-22 | 2000-11-15 | 김영환 | 반도체 장치의 분리구조 제조방법 |
JP2001118920A (ja) * | 1999-10-15 | 2001-04-27 | Seiko Epson Corp | 半導体装置およびその製造方法 |
KR100427153B1 (ko) * | 2001-01-04 | 2004-04-14 | 료덴 세미컨덕터 시스템 엔지니어링 (주) | 반도체 장치의 제조 방법 |
JP2007509492A (ja) * | 2003-10-16 | 2007-04-12 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 高性能の歪みcmosデバイス |
Also Published As
Publication number | Publication date |
---|---|
EP0660389A3 (de) | 1997-12-29 |
DE69429978D1 (de) | 2002-04-04 |
EP0660389B1 (de) | 2002-02-27 |
KR0179681B1 (ko) | 1999-04-15 |
DE69429978T2 (de) | 2002-10-02 |
EP0660389A2 (de) | 1995-06-28 |
US5766823A (en) | 1998-06-16 |
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