DE69126153D1 - Verfahren zur Herstellung von verbundenen Halbleiterplättchen - Google Patents

Verfahren zur Herstellung von verbundenen Halbleiterplättchen

Info

Publication number
DE69126153D1
DE69126153D1 DE69126153T DE69126153T DE69126153D1 DE 69126153 D1 DE69126153 D1 DE 69126153D1 DE 69126153 T DE69126153 T DE 69126153T DE 69126153 T DE69126153 T DE 69126153T DE 69126153 D1 DE69126153 D1 DE 69126153D1
Authority
DE
Germany
Prior art keywords
production
semiconductor wafers
bonded semiconductor
bonded
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126153T
Other languages
English (en)
Other versions
DE69126153T2 (de
Inventor
Tatsuo Ito
Masami Nakano
Yasuaki Nakazato
Atsuo Uchiyama
Takahiro Kida
Tokio Takei
Katsuo Yoshizawa
Masao Fukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2045776A external-priority patent/JPH0680624B2/ja
Priority claimed from JP2045778A external-priority patent/JPH0795505B2/ja
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69126153D1 publication Critical patent/DE69126153D1/de
Application granted granted Critical
Publication of DE69126153T2 publication Critical patent/DE69126153T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
DE1991626153 1990-02-28 1991-02-28 Verfahren zur Herstellung von verbundenen Halbleiterplättchen Expired - Fee Related DE69126153T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2045776A JPH0680624B2 (ja) 1990-02-28 1990-02-28 接合ウエーハの製造方法
JP2045778A JPH0795505B2 (ja) 1990-02-28 1990-02-28 接合ウエーハの製造方法

Publications (2)

Publication Number Publication Date
DE69126153D1 true DE69126153D1 (de) 1997-06-26
DE69126153T2 DE69126153T2 (de) 1998-01-08

Family

ID=26385840

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1991626153 Expired - Fee Related DE69126153T2 (de) 1990-02-28 1991-02-28 Verfahren zur Herstellung von verbundenen Halbleiterplättchen

Country Status (2)

Country Link
EP (1) EP0444943B1 (de)
DE (1) DE69126153T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
DE4210859C1 (de) * 1992-04-01 1993-06-09 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung Ev, 8000 Muenchen, De
JPH08501900A (ja) * 1992-06-17 1996-02-27 ハリス・コーポレーション 結合ウェーハの製法
JPH0799295A (ja) * 1993-06-07 1995-04-11 Canon Inc 半導体基体の作成方法及び半導体基体
US6484585B1 (en) 1995-02-28 2002-11-26 Rosemount Inc. Pressure sensor for a pressure transmitter
US5637802A (en) 1995-02-28 1997-06-10 Rosemount Inc. Capacitive pressure sensor for a pressure transmitted where electric field emanates substantially from back sides of plates
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
DE19803852C2 (de) * 1998-01-31 2003-12-18 Bosch Gmbh Robert Verfahren zur Herstellung beidseitig oxidierter Siliziumwafer
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
US6508129B1 (en) 2000-01-06 2003-01-21 Rosemount Inc. Pressure sensor capsule with improved isolation
US6505516B1 (en) 2000-01-06 2003-01-14 Rosemount Inc. Capacitive pressure sensing with moving dielectric
AU2629901A (en) 2000-01-06 2001-07-16 Rosemount Inc. Grain growth of electrical interconnection for microelectromechanical systems (mems)
US6520020B1 (en) 2000-01-06 2003-02-18 Rosemount Inc. Method and apparatus for a direct bonded isolated pressure sensor
US6561038B2 (en) 2000-01-06 2003-05-13 Rosemount Inc. Sensor with fluid isolation barrier
US20060276008A1 (en) * 2005-06-02 2006-12-07 Vesa-Pekka Lempinen Thinning
JP5183969B2 (ja) 2007-05-29 2013-04-17 信越半導体株式会社 Ｓｏｉウェーハのシリコン酸化膜形成方法
JP5418564B2 (ja) 2011-09-29 2014-02-19 信越半導体株式会社 貼り合わせｓｏｉウェーハの反りを算出する方法、及び貼り合わせｓｏｉウェーハの製造方法
DE102014219648A1 (de) 2014-09-29 2015-10-15 Carl Zeiss Smt Gmbh Verfahren zum Herstellen eines Spiegelelements

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6173345A (ja) * 1984-09-19 1986-04-15 Toshiba Corp 半導体装置
CA1251514A (en) * 1985-02-20 1989-03-21 Tadashi Sakai Ion selective field effect transistor sensor
NL8800953A (nl) * 1988-04-13 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderlichaam.

Also Published As

Publication number Publication date
EP0444943B1 (de) 1997-05-21
DE69126153T2 (de) 1998-01-08
EP0444943A1 (de) 1991-09-04

Similar Documents

Publication Publication Date Title
DE69325325D1 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE69431385D1 (de) Verfahren zur Herstellung von Silizium-Halbleiterplättchen
DE69132117D1 (de) Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen
DE69723338D1 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE69031447D1 (de) Verfahren zur Herstellung von MIS-Halbleiterbauelementen
DE69434536D1 (de) Verfahren zur Herstellung von halbleitenden Wafern
DE69132118T2 (de) Verfahren zur Herstellung von Isolationszonen für Halbleiteranordnungen
DE69233314D1 (de) Verfahren zur Herstellung von Halbleiter-Produkten
DE69130346D1 (de) Verfahren zur Herstellung von Halbleiteranordnungen
DE69222979T2 (de) Verfahren zur Herstellung von Mikrolinsen
DE69126156T2 (de) Verfahren zur Herstellung von Halbleiterbauelementen mit Floatinggates
DE3855469T2 (de) Verfahren zur Herstellung von Halbleiteranordnungen mit Gräben als Isolationszonen
DE69605867T2 (de) Verfahren zur Herstellung von Halbleiterscheiben mit spiegelglatter Oberfläche
DE69126153T2 (de) Verfahren zur Herstellung von verbundenen Halbleiterplättchen
DE69429978D1 (de) Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen
DE68913429D1 (de) Verfahren zur Herstellung von Silicium-Einkristallen.
DE69409780D1 (de) Verfahren zur Herstellung opto-elektrischer Halbleiterbauelemente
DE68916393T2 (de) Verfahren zur Herstellung von ebenen Wafern.
DE59304719D1 (de) Verfahren zur Herstellung von Polysilazanen
DE69302771D1 (de) Verfahren zur Herstellung von gesintertem Siliciumnitrid
DE3789680T2 (de) Verfahren zur Herstellung von Halbleiterbauelementen.
DE69115615T2 (de) Verfahren zur Herstellung von Ethylenaminen
DE69703600T2 (de) Verfahren zur Herstellung von Halbleiterscheiben
DE69133173T2 (de) Verfahren zur Herstellung von Knollen
DE69125203T2 (de) Zell-Bibliotheks-Verfahren zur Herstellung von integrierten Halbleiterschaltungen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee