DE69605867T2 - Verfahren zur Herstellung von Halbleiterscheiben mit spiegelglatter Oberfläche - Google Patents

Verfahren zur Herstellung von Halbleiterscheiben mit spiegelglatter Oberfläche

Info

Publication number
DE69605867T2
DE69605867T2 DE69605867T DE69605867T DE69605867T2 DE 69605867 T2 DE69605867 T2 DE 69605867T2 DE 69605867 T DE69605867 T DE 69605867T DE 69605867 T DE69605867 T DE 69605867T DE 69605867 T2 DE69605867 T2 DE 69605867T2
Authority
DE
Germany
Prior art keywords
mirror
production
smooth surface
semiconductor wafers
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69605867T
Other languages
English (en)
Other versions
DE69605867D1 (de
Inventor
Hisashi Masumura
Kiyoshi Suzuki
Hideo Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69605867D1 publication Critical patent/DE69605867D1/de
Application granted granted Critical
Publication of DE69605867T2 publication Critical patent/DE69605867T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
DE69605867T 1995-07-21 1996-07-19 Verfahren zur Herstellung von Halbleiterscheiben mit spiegelglatter Oberfläche Expired - Fee Related DE69605867T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP20751495 1995-07-21
JP20431196A JP3169120B2 (ja) 1995-07-21 1996-07-15 半導体鏡面ウェーハの製造方法

Publications (2)

Publication Number Publication Date
DE69605867D1 DE69605867D1 (de) 2000-02-03
DE69605867T2 true DE69605867T2 (de) 2000-05-18

Family

ID=26514407

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69605867T Expired - Fee Related DE69605867T2 (de) 1995-07-21 1996-07-19 Verfahren zur Herstellung von Halbleiterscheiben mit spiegelglatter Oberfläche

Country Status (6)

Country Link
US (1) US5827779A (de)
EP (1) EP0754785B1 (de)
JP (1) JP3169120B2 (de)
KR (1) KR100206094B1 (de)
DE (1) DE69605867T2 (de)
MY (1) MY132187A (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3620554B2 (ja) * 1996-03-25 2005-02-16 信越半導体株式会社 半導体ウェーハ製造方法
JPH10135164A (ja) * 1996-10-29 1998-05-22 Komatsu Electron Metals Co Ltd 半導体ウェハの製造方法
JPH10135165A (ja) * 1996-10-29 1998-05-22 Komatsu Electron Metals Co Ltd 半導体ウェハの製法
US6239039B1 (en) * 1997-12-09 2001-05-29 Shin-Etsu Handotai Co., Ltd. Semiconductor wafers processing method and semiconductor wafers produced by the same
US6214704B1 (en) 1998-12-16 2001-04-10 Memc Electronic Materials, Inc. Method of processing semiconductor wafers to build in back surface damage
DE19905737C2 (de) * 1999-02-11 2000-12-14 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe mit verbesserter Ebenheit
US6294469B1 (en) 1999-05-21 2001-09-25 Plasmasil, Llc Silicon wafering process flow
JP2001007064A (ja) * 1999-06-17 2001-01-12 Sumitomo Metal Ind Ltd 半導体ウエーハの研削方法
DE19928949A1 (de) * 1999-06-24 2001-01-04 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe
US6338805B1 (en) 1999-07-14 2002-01-15 Memc Electronic Materials, Inc. Process for fabricating semiconductor wafers with external gettering
US6200908B1 (en) 1999-08-04 2001-03-13 Memc Electronic Materials, Inc. Process for reducing waviness in semiconductor wafers
DE19956250C1 (de) 1999-11-23 2001-05-17 Wacker Siltronic Halbleitermat Kostengünstiges Verfahren zur Herstellung einer Vielzahl von Halbleiterscheiben
DE19958077A1 (de) * 1999-12-02 2001-06-13 Wacker Siltronic Halbleitermat Verfahren zur beidseitigen Politur von Halbleiterscheiben
DE10004578C1 (de) * 2000-02-03 2001-07-26 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe mit polierter Kante
DE10012840C2 (de) * 2000-03-16 2001-08-02 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Vielzahl von polierten Halbleiterscheiben
DE10196115B4 (de) * 2000-04-24 2011-06-16 Sumitomo Mitsubishi Silicon Corp. Verfahren zum Polieren eines Halbleiterwafers
KR100467009B1 (ko) * 2000-08-04 2005-01-24 샤프 가부시키가이샤 반도체 웨이퍼 표면의 오염을 방지할 수 있는 반도체웨이퍼의 박층화 방법 및 반도체 웨이퍼의 이면 연삭장치
CN1446142A (zh) * 2000-08-07 2003-10-01 Memc电子材料有限公司 用双面抛光加工半导体晶片的方法
US6709981B2 (en) 2000-08-16 2004-03-23 Memc Electronic Materials, Inc. Method and apparatus for processing a semiconductor wafer using novel final polishing method
WO2002035593A1 (fr) * 2000-10-26 2002-05-02 Shin-Etsu Handotai Co.,Ltd. Procede de production de plaquettes, appareil de polissage et plaquette
US6672943B2 (en) 2001-01-26 2004-01-06 Wafer Solutions, Inc. Eccentric abrasive wheel for wafer processing
US6672947B2 (en) * 2001-03-13 2004-01-06 Nptest, Llc Method for global die thinning and polishing of flip-chip packaged integrated circuits
US6632012B2 (en) 2001-03-30 2003-10-14 Wafer Solutions, Inc. Mixing manifold for multiple inlet chemistry fluids
US20060278912A1 (en) * 2004-09-02 2006-12-14 Luan Tran Selective polysilicon stud growth
JP4860192B2 (ja) * 2004-09-03 2012-01-25 株式会社ディスコ ウェハの製造方法
JP4820108B2 (ja) * 2005-04-25 2011-11-24 コマツＮｔｃ株式会社 半導体ウエーハの製造方法およびワークのスライス方法ならびにそれらに用いられるワイヤソー
JP2011523596A (ja) * 2008-05-06 2011-08-18 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． マイクロスケール光学構造を作製する方法
JP5401683B2 (ja) * 2008-08-01 2014-01-29 株式会社Ｓｕｍｃｏ 両面鏡面半導体ウェーハおよびその製造方法
DE102009025243B4 (de) * 2009-06-17 2011-11-17 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
JP6279593B2 (ja) * 2013-09-26 2018-02-14 株式会社フジミインコーポレーテッド 研磨用組成物、研磨用組成物の製造方法およびシリコンウェーハ製造方法
KR20180002571U (ko) 2017-02-17 2018-08-28 장기일 콤팩트 화장품 용기 체결구조
CN111644906B (zh) * 2020-06-02 2021-09-21 大连理工大学 一种高精度超薄光学零件增厚-光胶-对称减薄加工方法
CN114030093B (zh) * 2021-12-01 2023-02-28 长飞光纤光缆股份有限公司 一种晶体冷加工方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2655975B2 (ja) * 1992-09-18 1997-09-24 三菱マテリアル株式会社 ウェーハ研磨装置
JP2839801B2 (ja) * 1992-09-18 1998-12-16 三菱マテリアル株式会社 ウェーハの製造方法
US5643405A (en) * 1995-07-31 1997-07-01 Motorola, Inc. Method for polishing a semiconductor substrate

Also Published As

Publication number Publication date
JP3169120B2 (ja) 2001-05-21
JPH0997775A (ja) 1997-04-08
US5827779A (en) 1998-10-27
KR970008392A (ko) 1997-02-24
DE69605867D1 (de) 2000-02-03
EP0754785A1 (de) 1997-01-22
MY132187A (en) 2007-09-28
KR100206094B1 (ko) 1999-07-01
EP0754785B1 (de) 1999-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee