KR970008392A - 반도체 유리면웨이퍼의 제조방법 - Google Patents

반도체 유리면웨이퍼의 제조방법 Download PDF

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Publication number
KR970008392A
KR970008392A KR1019960029427A KR19960029427A KR970008392A KR 970008392 A KR970008392 A KR 970008392A KR 1019960029427 A KR1019960029427 A KR 1019960029427A KR 19960029427 A KR19960029427 A KR 19960029427A KR 970008392 A KR970008392 A KR 970008392A
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South Korea
Prior art keywords
glass surface
wafer
polishing
slicing
manufacturing
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KR1019960029427A
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KR100206094B1 (ko
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히사시 마스무라
기요시 스즈키
히데오 구도
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와다 다다시
신 에츠 한도타이 가부시키가이샤
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Publication of KR970008392A publication Critical patent/KR970008392A/ko
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Publication of KR100206094B1 publication Critical patent/KR100206094B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

높은 평탄도의 가공을 가능케하고, 또한 앞뒷 양면의 연마를 함으로써 이면의 칩핑에 의한 먼지방생을 억제하여 디바이스의 수율을 높일 수 있고, 또한 공정의 간략화를 도모함으로써, 생산성의 향상을 달성하고, 종래 방법에 비하여 낮은 생산코스트로 고품질의 웨이퍼가공을 가능케한 신규 반도체 유리면 웨이퍼의 제조방법을 제공한다.
단결정 인곳을 슬라이스하여서 얇은 원판형상의 웨이퍼를 얻는 슬라이스공정과 이 슬라이스공정에 의하여 얻어진 웨이퍼를 모서리 제거하는 모서리 제거공정과, 모서리 제거된 웨이퍼의 양면을 1차 유리면 연마하는 양면 1차 유리면 연마공정과 양면을 1차 유리면 연마한 웨이퍼의 편면을 마무리 유리면 연마하는 편면 마무리 유리면 연마공정을 포함한다.

Description

반도체 유리면웨이퍼의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체웨이퍼의 제조방법의 한 실시의 형태를 나타낸 플로우차트.

Claims (3)

  1. 반도체 단결정 인곳을 슬라이스하여서 얇은 원판형상의 웨이퍼를 얻는 슬라이스공정과, 이 슬라이스공정에 의하여 얻어진 웨이퍼를 모서리 제거하는 모서리 제거공정과, 모서리 제거된 웨이퍼의 양면을 1차 유리면 연마하는 양면 1차 유리면 연마공정과, 양면을 1차 유리면 연마한 웨이퍼의 편면을 마무리 유리면 연마하는 편면 마무리 유리면 연마공정을 포함하는 것을 특징으로 하는 반도체 유리면웨이퍼의 제조방법.
  2. 제1항에 있어서, 상기 양면 1차 유리면 연마공정에 있어서의 웨이퍼의 연마값이 60㎛ 이상인 것을 특징으로 하는 반도체 유리면웨이퍼의 제조방법.
  3. 제1항 또는 제2항에 있어서, 상기 양면 1차 유리면 연마공정에 있어서 사용하는 연마포가 아스카 C경도 80 이상의 경질 연마포인 것을 특징으로 하는 반도체 유리면웨이퍼의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960029427A 1995-07-21 1996-07-20 반도체 유리면웨이퍼의 제조방법 KR100206094B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP95-207514 1995-07-21
JP20751495 1995-07-21
JP20431196A JP3169120B2 (ja) 1995-07-21 1996-07-15 半導体鏡面ウェーハの製造方法
JP96-204311 1996-07-15

Publications (2)

Publication Number Publication Date
KR970008392A true KR970008392A (ko) 1997-02-24
KR100206094B1 KR100206094B1 (ko) 1999-07-01

Family

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Application Number Title Priority Date Filing Date
KR1019960029427A KR100206094B1 (ko) 1995-07-21 1996-07-20 반도체 유리면웨이퍼의 제조방법

Country Status (6)

Country Link
US (1) US5827779A (ko)
EP (1) EP0754785B1 (ko)
JP (1) JP3169120B2 (ko)
KR (1) KR100206094B1 (ko)
DE (1) DE69605867T2 (ko)
MY (1) MY132187A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214704B1 (en) 1998-12-16 2001-04-10 Memc Electronic Materials, Inc. Method of processing semiconductor wafers to build in back surface damage
US6338805B1 (en) 1999-07-14 2002-01-15 Memc Electronic Materials, Inc. Process for fabricating semiconductor wafers with external gettering

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JP3620554B2 (ja) * 1996-03-25 2005-02-16 信越半導体株式会社 半導体ウェーハ製造方法
JPH10135164A (ja) * 1996-10-29 1998-05-22 Komatsu Electron Metals Co Ltd 半導体ウェハの製造方法
JPH10135165A (ja) * 1996-10-29 1998-05-22 Komatsu Electron Metals Co Ltd 半導体ウェハの製法
US6239039B1 (en) * 1997-12-09 2001-05-29 Shin-Etsu Handotai Co., Ltd. Semiconductor wafers processing method and semiconductor wafers produced by the same
DE19905737C2 (de) * 1999-02-11 2000-12-14 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe mit verbesserter Ebenheit
US6294469B1 (en) 1999-05-21 2001-09-25 Plasmasil, Llc Silicon wafering process flow
JP2001007064A (ja) * 1999-06-17 2001-01-12 Sumitomo Metal Ind Ltd 半導体ウエーハの研削方法
DE19928949A1 (de) * 1999-06-24 2001-01-04 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe
US6200908B1 (en) 1999-08-04 2001-03-13 Memc Electronic Materials, Inc. Process for reducing waviness in semiconductor wafers
DE19956250C1 (de) 1999-11-23 2001-05-17 Wacker Siltronic Halbleitermat Kostengünstiges Verfahren zur Herstellung einer Vielzahl von Halbleiterscheiben
DE19958077A1 (de) * 1999-12-02 2001-06-13 Wacker Siltronic Halbleitermat Verfahren zur beidseitigen Politur von Halbleiterscheiben
DE10004578C1 (de) * 2000-02-03 2001-07-26 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Halbleiterscheibe mit polierter Kante
DE10012840C2 (de) * 2000-03-16 2001-08-02 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer Vielzahl von polierten Halbleiterscheiben
CN1203530C (zh) * 2000-04-24 2005-05-25 三菱住友硅晶株式会社 半导体晶片的制造方法
KR100467009B1 (ko) * 2000-08-04 2005-01-24 샤프 가부시키가이샤 반도체 웨이퍼 표면의 오염을 방지할 수 있는 반도체웨이퍼의 박층화 방법 및 반도체 웨이퍼의 이면 연삭장치
WO2002011947A2 (en) * 2000-08-07 2002-02-14 Memc Electronic Materials, Inc. Method for processing a semiconductor wafer using double-side polishing
US6709981B2 (en) 2000-08-16 2004-03-23 Memc Electronic Materials, Inc. Method and apparatus for processing a semiconductor wafer using novel final polishing method
EP1261020A4 (en) * 2000-10-26 2005-01-19 Shinetsu Handotai Kk PROCESS FOR PRODUCING PLATELETS, POLISHING APPARATUS AND PLATELET
US6672943B2 (en) 2001-01-26 2004-01-06 Wafer Solutions, Inc. Eccentric abrasive wheel for wafer processing
US6672947B2 (en) * 2001-03-13 2004-01-06 Nptest, Llc Method for global die thinning and polishing of flip-chip packaged integrated circuits
US6632012B2 (en) 2001-03-30 2003-10-14 Wafer Solutions, Inc. Mixing manifold for multiple inlet chemistry fluids
US20060278912A1 (en) * 2004-09-02 2006-12-14 Luan Tran Selective polysilicon stud growth
JP4860192B2 (ja) * 2004-09-03 2012-01-25 株式会社ディスコ ウェハの製造方法
JP4820108B2 (ja) * 2005-04-25 2011-11-24 コマツＮｔｃ株式会社 半導体ウエーハの製造方法およびワークのスライス方法ならびにそれらに用いられるワイヤソー
US20110062111A1 (en) * 2008-05-06 2011-03-17 Jong-Souk Yeo Method of fabricating microscale optical structures
JP5401683B2 (ja) * 2008-08-01 2014-01-29 株式会社Ｓｕｍｃｏ 両面鏡面半導体ウェーハおよびその製造方法
DE102009025243B4 (de) * 2009-06-17 2011-11-17 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
JP6279593B2 (ja) * 2013-09-26 2018-02-14 株式会社フジミインコーポレーテッド 研磨用組成物、研磨用組成物の製造方法およびシリコンウェーハ製造方法
KR20180002571U (ko) 2017-02-17 2018-08-28 장기일 콤팩트 화장품 용기 체결구조
CN111644906B (zh) * 2020-06-02 2021-09-21 大连理工大学 一种高精度超薄光学零件增厚-光胶-对称减薄加工方法
CN114030093B (zh) * 2021-12-01 2023-02-28 长飞光纤光缆股份有限公司 一种晶体冷加工方法

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JP2655975B2 (ja) * 1992-09-18 1997-09-24 三菱マテリアル株式会社 ウェーハ研磨装置
JP2839801B2 (ja) * 1992-09-18 1998-12-16 三菱マテリアル株式会社 ウェーハの製造方法
US5643405A (en) * 1995-07-31 1997-07-01 Motorola, Inc. Method for polishing a semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214704B1 (en) 1998-12-16 2001-04-10 Memc Electronic Materials, Inc. Method of processing semiconductor wafers to build in back surface damage
US6338805B1 (en) 1999-07-14 2002-01-15 Memc Electronic Materials, Inc. Process for fabricating semiconductor wafers with external gettering

Also Published As

Publication number Publication date
EP0754785A1 (en) 1997-01-22
DE69605867D1 (de) 2000-02-03
EP0754785B1 (en) 1999-12-29
JP3169120B2 (ja) 2001-05-21
DE69605867T2 (de) 2000-05-18
US5827779A (en) 1998-10-27
JPH0997775A (ja) 1997-04-08
MY132187A (en) 2007-09-28
KR100206094B1 (ko) 1999-07-01

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