KR910007102A - 두 보디의 결합 방법 - Google Patents

두 보디의 결합 방법 Download PDF

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Publication number
KR910007102A
KR910007102A KR1019900013601A KR900013601A KR910007102A KR 910007102 A KR910007102 A KR 910007102A KR 1019900013601 A KR1019900013601 A KR 1019900013601A KR 900013601 A KR900013601 A KR 900013601A KR 910007102 A KR910007102 A KR 910007102A
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KR
South Korea
Prior art keywords
layer
pure boron
high temperature
flat surface
connecting layer
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KR1019900013601A
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English (en)
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KR0185384B1 (ko
Inventor
하이스마 얀
아드리아누스 코르넬루스 마리아 스피링스 기예스베르투스
기예스베르투스 반 리로프 요젭
프레데릭 반 덴 베르그 헨드릭
Original Assignee
프레데릭 얀 스미트
엔. 브이. 필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of KR910007102A publication Critical patent/KR910007102A/ko
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Publication of KR0185384B1 publication Critical patent/KR0185384B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S228/00—Metal fusion bonding
    • Y10S228/903—Metal to nonmetal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Ceramic Products (AREA)
  • Thin Film Transistor (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

내용 없음

Description

두 보디의 결합 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 내지 제 4 도는 본 발명에 따른 두 보디의 여러 결합 공정 단계를 도시한 도면.

Claims (7)

  1. 제 1 보디 및 제 2 보디를 결합하는 방법으로서, 상기 제 1 보디에 플랫표면이 제공되고 실리콘 산화물층으로 코팅된 상기 제 2 보디에 또한 플랫표면이 제공되며, 붕소를 함유한 연결층이 상기 두 플랫표면중 최소한 하나에 인가되고, 고온에서 몇 시간동안 상기 플랫표면과 함께 상기 제 1 보디 및 제 2 보디가 서로에 대해 압착되며, 그 후 상기 두 보디중 하나가 물질 제거법에 의해 얇게 만들어지는 두 보디 결합 방법에 있어서, 순 붕소층이 연결층을 통해 사용되는 것을 특징으로 하는 두 보디 결합 방법.
  2. 제 1 항에 있어서, 상기 제 1 보디 및 제 2 보디가 서로 압착되기 전에 순 붕소로 구성된 상기 연결층이 연마 처리 과정을 리시브하는 것을 특징으로 하는 두 보디 결합 방법.
  3. 제 2 항에 있어서, 상기 연마 처리 과정이 실행되므로써 광학적으로 매끄러운 표면이 얻어지는 것을 특징으로 하는 두 보디 결합 방법.
  4. 제 3 항에 있어서, 상기 연결층이 상기 양 표면상에 제공되는 것을 특징으로 하는 두 보디 결합 방법.
  5. 상기 선행항중 어느 한 항에 있어서, 상기 제 1 보디 및 제 2 보디가 최소한 수분 및 최대한 네시간 동안 900 및 1050℃사이의 고온에서 1×10 및 1×10N/m 사이의 압력으로 서로에 대해 압착되는 것을 특징으로 하는 두 보디 결합 방법.
  6. 상기 선행항중 어느 한 항에 있어서, 순 붕소로 구성된 상기 층이 1과 200mm사이의 두께를 가지며, 실리콘 산화물층이 0.01과 2㎛ 사이의 두께를 가지는 것을 특징으로 하는 두 보디 결합 방법.
  7. 상기 선행항중 어느 한 항에 있어서, 상기 결합을 형성하는데 필요한 고온이 방사에 의해 상기 순 붕소를 가열하므로써 얻어지며 상기 방사가 상기 보디에 의해 투과되고 상기 순 붕소층에 의해 흡수되는 것을 특징으로 하는 두 보디 결합 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019900013601A 1989-09-12 1990-08-31 두 보디의 결합 방법 KR0185384B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8902271A NL8902271A (nl) 1989-09-12 1989-09-12 Werkwijze voor het verbinden van twee lichamen.
NL8902271 1989-09-12

Publications (2)

Publication Number Publication Date
KR910007102A true KR910007102A (ko) 1991-04-30
KR0185384B1 KR0185384B1 (ko) 1999-04-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900013601A KR0185384B1 (ko) 1989-09-12 1990-08-31 두 보디의 결합 방법

Country Status (6)

Country Link
US (1) US5054683A (ko)
EP (1) EP0417838B1 (ko)
JP (1) JP2857802B2 (ko)
KR (1) KR0185384B1 (ko)
DE (1) DE69015291T2 (ko)
NL (1) NL8902271A (ko)

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KR100857224B1 (ko) * 2008-03-28 2008-09-05 주식회사 코디에스 레이저를 이용한 프로브카드 제조장치 및 방법
KR100857228B1 (ko) * 2008-03-28 2008-09-05 주식회사 코디에스 프로브카드 제조장치 및 방법

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JPH04365377A (ja) * 1991-06-13 1992-12-17 Agency Of Ind Science & Technol 半導体装置
JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
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US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
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US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
US6015980A (en) * 1996-03-08 2000-01-18 The Regents Of The University Of California Metal layered semiconductor laser
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JP6180162B2 (ja) * 2013-04-09 2017-08-16 アルバック成膜株式会社 基板の貼り合わせ方法および貼り合わせ基板
US9347890B2 (en) 2013-12-19 2016-05-24 Kla-Tencor Corporation Low-noise sensor and an inspection system using a low-noise sensor
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KR100857228B1 (ko) * 2008-03-28 2008-09-05 주식회사 코디에스 프로브카드 제조장치 및 방법

Also Published As

Publication number Publication date
NL8902271A (nl) 1991-04-02
JP2857802B2 (ja) 1999-02-17
US5054683A (en) 1991-10-08
DE69015291T2 (de) 1995-07-20
EP0417838B1 (en) 1994-12-21
DE69015291D1 (de) 1995-02-02
KR0185384B1 (ko) 1999-04-15
EP0417838A1 (en) 1991-03-20
JPH03105910A (ja) 1991-05-02

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