EP0988651B1 - Structure de transistor LDMOS à contact de source en tranchée - Google Patents

Structure de transistor LDMOS à contact de source en tranchée Download PDF

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EP0988651B1
EP0988651B1 EP98926453.6A EP98926453A EP0988651B1 EP 0988651 B1 EP0988651 B1 EP 0988651B1 EP 98926453 A EP98926453 A EP 98926453A EP 0988651 B1 EP0988651 B1 EP 0988651B1
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region
trench
source
transistor structure
doped
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EP0988651A1 (fr
EP0988651A4 (fr
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Francois Hebert
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F Poszat HU LLC
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Rovec Acquisitions Ltd LLC
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Definitions

  • This invention relates generally to insulated gate field effect transistors (IGFET) such as the metal oxide silicon (MOS) transistor, and more particularly the invention relates to a lateral IGFET and MOS (LDMOS) transistor having a reduced layout area and pitch and reduced grounded source resistance and capacitance in power applications.
  • IGFET insulated gate field effect transistors
  • MOS metal oxide silicon
  • LDMOS lateral IGFET and MOS
  • the laterally diffused MOS transistor is used in power-applications for low-side switches as well as for RF/microwave power amplifiers.
  • the devices are typically fabricated in an epitaxial silicon layer (P-) on a more highly doped silicon substrate (P+).
  • P- epitaxial silicon layer
  • P+ more highly doped silicon substrate
  • a grounded source configuration is achieved by deep P+ sinker diffusion from the source region to the P+ substrate, which is grounded.
  • the diffused sinker has a lateral diffusion which increases the necessary width of the source contact.
  • the deep P+ sinker must be kept away from the gate and channel regions in order to achieve a controlled threshold voltage.
  • the P+ sinker in an epitaxial layer having 5 ⁇ m thickness, the P+ sinker must be greater than 5 ⁇ m in depth and will have greater than 4 ⁇ m lateral diffusion on all sides.
  • the pitch of a two transistor cell having a common source or drain is on the order of 30 ⁇ m.
  • the heat budget for a diffused sinker causes dopant out diffusion from the heavily doped substrate, which increases parasitic capacitance of the device.
  • the present invention is directed to a process and resulting LDMOS structure having reduced pitch, source resistance, and capacitance.
  • EP-A-0209949 relates to the fabrication of lateral and vertical DMOS transistors.
  • a trench is cut into an N+ source region formed in a P well and the source contact is placed in the trench. This is intended to reduce the size of the transistor, without reducing the surface area of the source contact.
  • JP-A-55162270 , JP-A-58122781 and JP-A-6151846 further disclose lateral MOS transistors having trenched source contacts extending to a subtrate.
  • US-A-5627394 relates to a lateral DMOS transistor.
  • An N+ source region is formed in a P well.
  • An extended N drain region is formed in contact with an underside of a gate insulator portion which is thicker than a gate insulator portion overlying the well region.
  • the diffused sinker region of an LDMOS transistor is replaced by a trench in the source contact area of the epitaxial layer which extends toward the underlying substrate.
  • a shallow doped sinker region is diffused into the bottom surface of the trench to contact the underlying substrate.
  • the trench is then filled with a conductive material plug.
  • the reduced P+ diffusion permits reduced cell pitch, and the reduced thermal budget, as compared to a diffused sinker region, reduces the lateral diffusion and the up-diffusion of the highly doped substrate. Accordingly, parasitic capacitance is reduced and source contact resistance is reduced due to the highly conductive plug.
  • a transistor structure in accordance with the invention is set out in claim 1.
  • a corresponding fabrication method is defined in independent claim 10.
  • Specific embodiments are defined in the dependent claims.
  • Fig. 1 is a section view of a diffused sinker laterally diffused MOS transistor in accordance with the prior art
  • Fig. 2 is a plan view of the transistor.
  • the device is fabricated in a P- epitaxial layer 10 grown on a P+ silicon substrate 12 which in operation is grounded.
  • the transistor includes an N+ source region 14, and a drain region including an N+ region 16 and an N- drift region 18.
  • a gate electrode 20 is positioned on a silicon oxide insulating layer 22 above the channel region 24 between the source 14 and N- drift region 18 of the drain region.
  • the channel region 24 is formed from the P- epitaxial layer into which the source region and N- drift region are diffused.
  • a P+ sinker region 26 is diffused from the surface of the epitaxial layer 10 towards or to the P+ substrate 12 and then heated to diffuse the dopant and provide a conductive path from the source region to the substrate.
  • the P+ sinker region For an epitaxial layer having a thickness of approximately 5 ⁇ m, the P+ sinker region must be greater than 5 ⁇ m in depth, and the lateral diffusion from heat treatment will be greater than 4 ⁇ m on all sides.
  • the total cell pitch (2 transistors per cell) is on the order of 30 ⁇ m with the total top source contact width of at least 10 ⁇ m including the surface contact width and twice the lateral diffusion.
  • FIG. 2 is a plan view of the device of Fig. 1 illustrating the lateral dimensions for a one-half cell pitch (1 transistor).
  • the source and drain contacts and metal are 2 ⁇ m, the drain drift region is on the order of 4 ⁇ m, the silicon gate electrode is 3 ⁇ m, ground contact to gate electrode spacing is 2 ⁇ m, and the P+ lateral diffusion is 4 ⁇ m.
  • the P+ sinker region as illustrated in Figs. 1 and 2 sis replaced by a shallow conductive trench formed in, and extending partly throughs the epitaxial layer into which P+ dopant is formed and then the trench is filled with a conductive material.
  • the resulting source contact significantly reduces the lateral dimension necessary for the P+ sinker contact.
  • the conductive material plug in the trench reduces the vertical resistance of the contact, and the reduced thermal budget requirements limits any lateral diffusion and minimizes up-diffusion from the P+ substrate.
  • Figs. 3 and 4 are a section view and plan view, respectively, of an embodiment of the present invention comprising a shallow conductive trench, and like elements in Figs. 1 , 2 and Figs. 3 , 4 have the same reference numerals.
  • the P+ sinker region 26 of Fig. 1 is replaced by a conductive material plug 30 formed in a trench in the epitaxial layer and a P+ shallow sinker region 32 formed at the bottom and on the sidewalls of the trench.
  • the oxide insulating layer 22 separating the gate electrode from the channel region is increased in thickness over the N- drift region 18 of the drain region.
  • one-half cell pitch has been reduced from 15 ⁇ m to 11 ⁇ m including one-half of the 2 ⁇ m drain contact, 4 ⁇ m drift region, 3 ⁇ m polysilicon gate electrode, 2 ⁇ m ground contact to gate electrode spacing, and one-half of the 2 ⁇ m source contact of metal.
  • the shallow conductive trench minimizes the depth of the P+ sinker region which results in lower resistance, lower thermal budget, reduced P+ substrate up diffusion, and reduced lateral diffusion and cell pitch. Tighter cell pitch is realized since the use of a conductive trench minimizes the amount of P+ diffusion required to reach the P+ substrate for the grounded source contact.
  • the conductive material plug has a lower resistivity than P+ doped silicon, and parasitic capacitance is reduced by minimizing the up diffusion from the P+ substrate.
  • Figs. 5A-5E are section views illustrating steps in fabricating the transistor structure of Figs. 3 , 4 .
  • the starting material can be N- epitaxial layer on P+ substrate, P-epitaxial layer on P+ substrate (as illustrated), N- epitaxial layer on P- epitaxial layer on a P+ substrate.
  • a silicon oxide layer 40 is grown on the surface of the epitaxial layer 10, followed by a trench mask and oxide etch.
  • the trench 42 is then etched to a depth of approximately one-half of the epitaxial layer thickness using either photoresist or oxide as a hard mask material and fluorine, bromine, and/or chlorine base chemistries for dry etching.
  • a P+ shallow sinker region 44 is implanted at the bottom of the trench using 1E15-1E16 dose of boron or BF2 at 10-100 KeV with zero tilt preferred.
  • any native oxide is removed from the trench sidewalls, and a conformal conductive material is then deposited to fill the trench 42.
  • the conductive trench fill material can be undoped polysilicon, in-situ doped polysilicon, tungsten (W), or tungsten silicide (WSi x ) for example.
  • the film can be deposited by chemical vapor deposition and sputtering.
  • anisotropic etchback of the conductive trench fill material leaves the material solely in the trench thereby forming the conductive material plug 30.
  • Reactive ion etching with fluorinated or chlorinated chemistries can be used.
  • Optional P+ doping can be employed particularly if polysilicon is used as the conductive trench fill material. Since only the trench fill material is exposed through the silicon oxide layer, there is no need for a doping mask.
  • silicon nitride deposition (0,05 to 0,2 ⁇ m) forms nitride layer 46 and diffuses the P+ shallow sinker region 44 into the underlying substrate with limited sidewall diffusion from the doped conductive material in the trench.
  • a sinker drive of 900-1150°C for 20-500 minutes provides field oxide growth 48 of 0,5-3 ⁇ m with the P+ shallow sinker region diffusing to intersect the P+ substrate.
  • the device is completed with gate oxidation and gate material deposition (polysilicon or polycide), gate mask and etch followed by channel mask, channel implant and channel diffusion.
  • the N- drift mask and implant and N+ source and drain contact mask and implant are then formed followed by deposition of a dielectric, contact mask and contact etch, and finally, metalization of the source and drain contacts 50 and 52.
  • Fig. 6 is a section view of an example not part of the invention which employs a deep conductive trench. Again, like elements in Fig. 3 and Fig. 6 have the same reference numerals.
  • the trench can be formed as before or after field oxidation or before or after channel drive since there is no need for the P+ shallow or deep sinker diffusions. Further reduction in cell pitch is realized since there will be no lateral diffusion of the P+ dopant from the trench.
  • Fig. 7 is a section view of another example not part of the invention in which the trench structure is formed by anisotropic wet chemical etching (KOH) rather than dry etching.
  • KOH anisotropic wet chemical etching
  • a shallow or deep V-groove results which is filled with a conductive material plug 30, as shown.
  • trench source contact structures for a lateral DMOS transistor which reduce source contact resistance and parasitic capacitance while also reducing the pitch of the resulting LDMOS structure.

Claims (13)

  1. Structure de transistor comportant
    a) un substrat semi-conducteur dopé (12), qui peut être connecté à la terre lors du fonctionnement du transistor,
    b) une couche semi-conductrice épitaxiale dopée (10) formée sur le substrat, la couche ayant une surface,
    c) une région de source (14) et une région de drain (16, 18) formées dans la couche épitaxiale avec une région de canal (24) entre elles,
    d) une électrode de grille (20) formée sur une couche isolante (22) au-dessus de la région de canal, et
    e) un contact de source s'étendant depuis la surface de la couche épitaxiale jusque dans la couche épitaxiale, le contact de source comprenant une tranchée (42) remplie d'un fiche de matériau conducteur (30), la tranchée s'étendant partiellement au travers de la couche épitaxiale, et une région réceptrice dopée (32, 44) qui étend le contact depuis la tranchée jusqu'au substrat semi-conducteur de manière à connecter le substrat semi-conducteur au niveau de la région de source.
  2. Structure de transistor selon la revendication 1, dans laquelle le transistor est un transistor MOS à diffusion latérale.
  3. Structure de transistor selon la revendication 2, dans laquelle la région de drain comprend une région fortement dopée (16) et une région de dérive légèrement dopée (18) s'étendant jusqu'à la région de canal.
  4. Structure de transistor selon la revendication 3, dans laquelle la couche isolante sous l'électrode de grille s'étend au-dessus de la région de dérive, l'épaisseur de la couche isolante étant supérieure au-dessus de la région de dérive par rapport à au-dessus de la région de canal.
  5. Structure de transistor selon la revendication 1, dans laquelle le matériau conducteur est sélectionné dans le groupe constitué par du polysilicium, un métal réfractaire, et un siliciure métallique réfractaire.
  6. Structure de transistor selon la revendication 5, dans laquelle ladite électrode de grille comporte du polysilicium dopé.
  7. Structure de transistor selon la revendication 6, et comprenant par ailleurs des contacts métalliques (52, 50) au niveau de la région de drain, de la région de source, et du contact de source.
  8. Structure de transistor selon la revendication 7, dans laquelle un contact métallique (50) est formé au niveau de la région de source et du contact de source.
  9. Structure de transistor selon la revendication 1, dans laquelle le substrat semi-conducteur est plus fortement dopé que la couche semi-conductrice épitaxiale.
  10. Procédé de fabrication d'une structure de transistor comportant les étapes consistant à :
    a) mettre en oeuvre un substrat semi-conducteur dopé (12) qui peut être connecté à la terre lors du fonctionnement du transistor, et une couche semi-conductrice épitaxiale dopée (10) sur celui-ci,
    b) graver une tranchée (42) dans la couche semi-conductrice épitaxiale pour mettre en oeuvre un contact de source, la tranchée s'étendant partiellement au travers de la couche épitaxiale, et mettre en oeuvre une région réceptrice dopée (44) pour étendre le contact depuis la tranchée jusqu'au substrat semi-conducteur de manière à connecter le substrat semi-conducteur au niveau de la région de source ;
    c) remplir la tranchée d'une fiche de matériau conducteur (30),
    d) former des régions de source (14) et de drain (16, 18) espacées dans la couche épitaxiale avec une région de canal (24) entre elles,
    e) former une électrode de grille (20) sur une couche isolante (22) au-dessus de la région de canal, et
    f) former un contact ohmique (52) au niveau de la région de drain et un contact ohmique (50) au niveau de la région de source et de la fiche de matériau conducteur.
  11. Procédé selon la revendication 10, dans lequel l'étape b) comporte un processus de gravure sèche.
  12. Procédé selon la revendication 11, dans lequel le processus de gravure sèche est sélectionné parmi la gravure au plasma et la gravure ionique réactive.
  13. Procédé selon la revendication 10, dans lequel l'étape b) comporte un processus de gravure humide.
EP98926453.6A 1997-06-10 1998-06-10 Structure de transistor LDMOS à contact de source en tranchée Expired - Lifetime EP0988651B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/872,589 US5869875A (en) 1997-06-10 1997-06-10 Lateral diffused MOS transistor with trench source contact
US872589 1997-06-10
PCT/US1998/011885 WO1998057379A1 (fr) 1997-06-10 1998-06-10 Transistor mos a diffusion laterale a contact tranche source

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EP0988651A1 EP0988651A1 (fr) 2000-03-29
EP0988651A4 EP0988651A4 (fr) 2007-10-17
EP0988651B1 true EP0988651B1 (fr) 2013-09-25

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EP (1) EP0988651B1 (fr)
JP (1) JP4778127B2 (fr)
KR (1) KR100476816B1 (fr)
AU (1) AU7828898A (fr)
WO (1) WO1998057379A1 (fr)

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EP0988651A1 (fr) 2000-03-29
JP2002504267A (ja) 2002-02-05
KR20010006411A (ko) 2001-01-26
KR100476816B1 (ko) 2005-03-17
WO1998057379A1 (fr) 1998-12-17
JP4778127B2 (ja) 2011-09-21
AU7828898A (en) 1998-12-30
EP0988651A4 (fr) 2007-10-17
US5869875A (en) 1999-02-09
WO1998057379A9 (fr) 1999-04-08

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