CN114975609A - 横向双扩散的金属氧化物半导体场效晶体管及其制作方法 - Google Patents

横向双扩散的金属氧化物半导体场效晶体管及其制作方法 Download PDF

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CN114975609A
CN114975609A CN202110207876.3A CN202110207876A CN114975609A CN 114975609 A CN114975609 A CN 114975609A CN 202110207876 A CN202110207876 A CN 202110207876A CN 114975609 A CN114975609 A CN 114975609A
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semiconductor substrate
depth
source
electrode
source electrode
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冯仲彦
郭镇铵
邓经纬
赖柏均
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US17/224,108 priority patent/US11616139B2/en
Priority to US17/884,599 priority patent/US11670713B2/en
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Abstract

本发明公开一种横向双扩散的金属氧化物半导体场效晶体管及其制作方法，其中该横向双扩散的金属氧化物半导体场效晶体管包含一半导体基底，一阱区设置于半导体基底中，一基体区设置于阱区中，一第一栅极电极设置于半导体基底上，一源极电极设置在第一栅极电极的一侧，其中源极电极包含一源极接触区和多个插栓，并且插栓和源极接触区相连，插栓延伸插入半导体基底中，一第一漏极电极设置在第一栅极电极相对源极电极的另一侧。

Description

横向双扩散的金属氧化物半导体场效晶体管及其制作方法
技术领域
本发明涉及一种横向双扩散的金属氧化物半导体场效晶体管及其制作方法，特别是涉及一种具有多个插栓(via)插入源极位置的横向双扩散的金属氧化物半导体场效晶体管及其制作方法。
背景技术
在具有高压处理能力的功率元件中，双扩散金属氧化物半导体导体(double-diffused MOS，DMOS)晶体管元件持续受到重视。常见的DMOS晶体管元件有垂直双扩散金属氧化物半导体导体(vertical double-diffused MOS，VDMOS)与横向双扩散金属氧化物半导体导体(lateral double-diffused MOS，以下简称为LDMOS)晶体管元件。而LDMOS晶体管元件因具有较高的操作频宽与操作效率，以及易与其他集成电路整合的平面结构，现已广泛地应用于高电压操作环境中，如中央处理器电源供应(CPU power supply)、电源管理系统(power management system)、直流/交流转换器(AC/DC converter)以及高功率或高频段的功率放大器等等
为了增加LDMOS晶体管元件线性区的漏极电流量(linear drain current)，目前业界会把P型基体(body)设置在较浅处，但如此一来会使得基底上累积电荷造成漏电流。
发明内容
有鉴于此，本发明提供一种双扩散的金属氧化物半导体场效晶体管(LDMOS)，在提升线性区的漏极电流量的同时避免漏电流。
根据本发明的一优选实施例，一种横向双扩散的金属氧化物半导体场效晶体管包含一半导体基底，一阱区设置于半导体基底中，一基体区设置于阱区中，一第一栅极电极设置于半导体基底上，一源极电极设置在第一栅极电极的一侧，其中源极电极包含一源极接触区和多个插栓(via)，并且插栓和源极接触区相连，插栓延伸插入半导体基底中，以及一第一漏极电极设置在第一栅极电极相对源极电极的另一侧。
根据本发明的另一优选实施例，一种横向双扩散的金属氧化物半导体场效晶体管的制作方法包含提供一半导体基底，其中一阱区设置于半导体基底中，一基体区设置于阱区中，一栅极电极设置于半导体基底上，一漏极和一源极位于栅极电极两侧的半导体基底中，然后形成一金属硅化物阻挡层覆盖源极，其中金属硅化物阻挡层包含多个长条形轮廓，接着形成一介电层覆盖半导体基底，之后蚀刻介电层和金属硅化物阻挡层以形成一源极接触洞位于源极正上方，其中源极接触洞包含一沟槽和多个通孔，各个通孔和沟槽相连，各个通孔穿透金属硅化物阻挡层并且插入源极，沟槽只位于介电层中，最后形成一导电层填入源极接触洞，以形成一源极电极。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图2C为本发明的第一优选实施例所绘示一种LDMOS的制作方法的示意图；其中：
图2A为图2中沿着切线AA’所绘示的侧示图；
图2B为图2中沿着切线BB’所绘示的侧示图；
图2C为图2中沿着切线CC’所绘示的侧示图；
图3至图5A为本发明的第二优选实施例所绘示一种LDMOS的制作方法的示意图；其中：
图4A为图4中沿着切线DD’所绘示的侧示图；
图5A为图5中沿着切线EE’所绘示的侧示图。
主要元件符号说明
10:半导体基底
12a:第一栅极电极
12b:第二栅极电极
14a:第一漏极
14b:第二漏极
16:源极
18:金属硅化物阻挡层
18a:长条形轮廓
18b:长条形轮廓
20:阱区
22:基体区
24:金属硅化物
26:介电层
28:源极接触洞
28a:沟槽
28b:通孔
30a:第一漏极接触洞
30b:第二漏极接触洞
32a:掺杂区
32b:掺杂区
34:源极电极
34a:源极接触区
34b:插栓
36a:第一漏极电极
36b:第二漏极电极
100:LDMOS
200:LDMOS
D1:第一深度
D2:第二深度
D3:第三深度
S:间隔
具体实施方式
图1至图2C为根据本发明的第一优选实施例所绘示一种LDMOS的制作方法。图2A为图2中沿着切线AA’所绘示的侧示图。图2B为图2中沿着切线BB’所绘示的侧示图。图2C为图2中沿着切线CC’所绘示的侧示图。
如图1所示，首先提供一半导体基底10，一第一栅极电极12a和一第二栅极电极12b设置于半导体基底10上，第一栅极电极12a和第二栅极电极12b可以各自包含一上盖层(图未示)和一栅极介电层(图未示)。一第一漏极14a及一源极16位于第一栅极电极12a两侧的半导体基底10中，源极16位于第一栅极电极12a和第二栅极电极12b之间，在第二栅极电极12b相对于源极16的一侧设置有一第二漏极14b。然后形成一金属硅化物阻挡层18覆盖源极16，值得注意的是在源极16位置的金属硅化物阻挡层18包含多个长条形轮廓18a/18b，每个长条形轮廓18a/8b之间具有一间隔S，使得源极16没有完全被金属硅化物阻挡层18覆盖，部分的半导体基底10从间隔S曝露出来，而第一漏极14a和第二漏极14b则是完全没有被金属硅化物阻挡层18覆盖。此外请先参阅图2A，一阱区20设置于半导体基底10中，一基体区22设置于阱区20中，基体区22的底面和半导体基底10的上表面之间具有一第一深度D1，阱区20的底面和半导体基底10的上表面之间具有一第二深度D2，第二深度D2大于第一深度D1，也就是阱区20的底面较基体区22的底面深。
接着如图2、图2A、图2B和图2C所示，进行一金属硅化制作工艺以在源极16、第一漏极14a和第二漏极14b上形成金属硅化物24，形成一介电层26覆盖半导体基底10，为了图示简洁，在图2中省略介电层26。之后蚀刻介电层26、金属硅化物阻挡层18和源极16以形成一源极接触洞28位于源极16正上方的介电层28中并且延伸插入源极16，其中源极接触洞28包含一沟槽28a和多个通孔28b，各个通孔28b和沟槽28a相连，各个通孔28a穿透金属硅化物阻挡层18并且插入源极16，并且沟槽28a只位于介电层26中。
在形成前述沟槽28a时，在同一个蚀刻步骤中一并蚀刻在第一漏极14a和第二漏极14b上的介电层26以形成一第一漏极接触洞30a和第二漏极接触洞30b，由第一漏极接触洞30a曝露出第一漏极14a上的金属硅化物24，由第二漏极接触洞30b曝露出第二漏极14b上的金属硅化物24，当第一漏极接触洞30a、第二漏极接触洞30b和沟槽28a形成在介电层26中之后，也就是介电层26被第一漏极接触洞30a、第二漏极接触洞30b和沟槽28a贯穿后，更换蚀刻剂接续蚀刻源极16上的金属硅化物阻挡层18和金属硅化物阻挡层18下方的半导体基底10，以在源极16位置的金属硅化物阻挡层18和半导体基底10中形成数个通孔28b插入源极16，在图示中以虚线分隔通孔28b和沟槽28a。在完成通孔28b之后进行一离子掺杂制作工艺，在各个通孔28b下方的阱区20中各自形成一掺杂区32b。
根据本发明的另一优选实施例，也可以先依序蚀刻介电层28、金属硅化物阻挡层18和半导体基底10以在源极16位置形成数个通孔28b之后，再度蚀刻介电层26以在源极16上方的介电层26中形成沟槽28a、在第一漏极14a上方形成第一漏极接触洞30a和在第二漏极14b上方形成第二漏极接触洞30b。
接着，形成一导电层填入源极接触洞28、第一漏极接触洞30a和第二漏极接触洞30b，填入源极接触洞28的导电层作为源极电极34，在源极接触洞28的各个通孔28b中的导电层形成多个插栓(via)34b，在源极接触洞28的沟槽28a中的导电层形成一个源极接触区34a，源极接触区34a和各个插栓34b相连，但各个插栓34b之间彼此不接触。另外，在第一漏极接触洞30a中的导电层作为一第一漏极电极36a，在第二漏极接触洞30b中的导电层作为一第二漏极电极36b。至此本发明的LDMOS 100业已完成。
下文将以图2、图2A、图2B和图2C来说明利用本发明的第一优选实施例所制作的LDMOS的结构。如图2、图2A、图2B和图2C所示，一种横向双扩散的金属氧化物半导体场效晶体管100包含一半导体基底10，一阱区20设置于半导体基底10中，一基体区22设置于阱区20中，一第一栅极电极12a和一第二栅极电极12b设置于半导体基底10上，第一栅极电极12a和第二栅极电极12b可以各自包含一上盖层(图未示)和一栅极介电层(图未示)。一第一漏极14a和一源极16位于第一栅极电极12a两侧的半导体基底10中，源极16位于第一栅极电极12a和第二栅极电极12b之间的半导体基底10中，在第二栅极电极12b相对于源极16的一侧设置有一第二漏极14b。此外，基体区22的底面和半导体基底10的上表面之间具有一第一深度D1，阱区22的底面和半导体基底10的上表面之间具有一第二深度D2，第二深度D2大于第一深度D1，也就是阱区20的底面较基体区22的底面深。半导体基底10为第一导电型态，阱区20为第二导电型态，基体区22为第一导电型态，第一漏极14a和第二漏极14b都为第二导电型态，源极16主要是第二导电型态的区域，但在第二导电型态的区域中有另外设置有一第一导电型态的掺杂区32a。第一导电型态和第二导电型态不同，在本实施例中，第一导电型态较佳为P型，第二导电型态佳为N型。在不同的实施例中，第一导电型态可以为N型，第二导电型态佳为P型。
一金属硅化物24覆盖源极16、第一漏极14a和第二漏极14b，值得注意的是：在源极16上设置有金属硅化物阻挡层18，金属硅化物阻挡层18包含多个长条形轮廓18a/18b，各个长条形轮廓18a/18b之间具有一间隔S(请参阅图1以获得长条形轮廓18a/18b和间隔S的位置)，所以金属硅化物24会覆盖在间隔S上。在第一漏极14a和第二漏极14b上没有金属硅化物阻挡层18，因此金属硅化物24会完全覆盖第一漏极14a和第二漏极14b。
一源极电极34设置在第一栅极电极12a的一侧，源极电极34包含一源极接触区34a和多个插栓34b，并且多个插栓34b和源极接触区34a相连，各个插栓34b延伸插入位于源极16位置的半导体基底10中，详细来说各个插栓34b分别穿透金属硅化物阻挡层18插入源极16，而源极接触区34a则是完全位于金属硅化物24上，也就是说金属硅化物24位于源极接触区34a和半导体基体10的上表面之间。另外插栓34b的数量需二根以上，在第一较佳实施例中以三根插栓34b为例，但插栓34b的数量可以依据不同需求调整。此外，各个插栓34的一末端和半导体基底10的上表面之间具有一第三深度D3，第三深度D3至少要等于前述的第一深度D1，也就是插栓34b的末端至少需和基体区22的底面一样深；在其它实施例中第三深度D3可以大于第一深度D1，也就是说插栓34b的末端比基体区22的底面还要深。多个掺杂区32b分别位于各个插栓34b的下方的阱区20中，各个掺杂区32b为第一导电型态。多个掺杂区32b彼此间不接触。
一第一漏极电极36a设置在第一栅极电极12a相对源极电极34a的另一侧，第一漏极电极36a接触第一漏极14a上的金属硅化物24，一第二漏极电极36b设置在第二栅极电极12b相对源极电极34的另一侧，并且第二漏极电极36b接触第二漏极14b上的金属硅化物24。第一漏极电极36a和第二漏极电极36b都没有贯穿金属硅化物24或是插入第一漏极14a或第二漏极14b。源极电极34、第一漏极电极36a和第二漏极电极36b可以包含Cu、W、Al、Ti、Ta、TiN、WN或其它导电材料。
图3至图5A为根据本发明的第二优选实施例所绘示一种LDMOS的制作方法。图4A为图4中沿着切线DD’所绘示的侧示图。图5A为图5中沿着切线EE’所绘示的侧示图。在第二优选实施例中具有相同位置和功能的元件，将使用第一优选实施例中的元件标号，且相同的部分将不重复赘述。
如图3所示，一种横向双扩散的金属氧化物半导体场效晶体管的制作方法包含提供一半导体基底10，一第一栅极电极12a和一第二栅极电极12b设置于半导体基底10上。请先参阅图4A，在半导体基底10中设置有一阱区20，一基体区22设置于阱区20中。请再度参阅图3，一第一漏极14a及一源极16位于第一栅极电极12a两侧的半导体基底10中，源极16位于第一栅极电极12a和第二栅极电极12b之间的半导体基底10中，在第二栅极电极12b相对于源极16的一侧设置有一第二漏极14b。接着进行一金属硅化制作工艺，形成一金属硅化物24覆盖源极16、第一漏极14a和第二漏极14b。
如图4和图4A所示，形成一介电层26覆盖第一栅极电极12a、第二栅极电极12b、第一漏极14a、第二漏极14b和源极16，然后进行一第一蚀刻制作工艺，蚀刻介电层26、金属硅化物层24以及半导体基底10以形成多个通孔28b穿透介电层26、金属硅化物24并且插入源极16，如图5和图5A所示，进行一第二蚀刻制作工艺，蚀刻介电层24以形成一沟槽28a、一第一漏极接触洞30a和第二漏极接触洞30b，沟槽28a位于在源极16的正上方的介电层26中，并且沟槽28a和多个通孔28b相连构成一源极接触洞28，部分的金属硅化物24由沟槽28a曝露出来，第一漏极接触洞30a和第二漏极接触洞30b分别位于第一漏极14a和第二漏极14b上，金属硅化物24由第一漏极接触洞30a和第二漏极接触洞30b曝露出来。
接着进行一离子掺杂制作工艺，在各个通孔28b下方的阱区20中各自形成一掺杂区32b。然后请参阅图5A，形成一导电层填入源极接触洞28、第一漏极接触洞30a、第二漏极接触洞30b，位于源极接触洞28中的导电层构成一源极电极34并且源极电极34和金属硅化物24相连接。在第一漏极接触洞30a和第二漏极接触洞30b的导电层分别构成一第一漏极电极36a和一第二漏极电极36b。至此本发明的LDMOS 200业已完成。
下文将以图2A、图2C、图5和图5A来说明利用本发明的第二优选实施例所制作的LDMOS的结构，其中具有相同位置和功能的元件，将使用第一优选实施例中的元件标号，且相同的部分将不重复赘述。第二优选实施例的LDMOS 200和第一优选实施例的LDMOS 100的不同之处在于：第二优选实施例的LDMOS 200中没有金属硅化物阻挡层。其余元件位置和材料都与第一较优选施例相同，因此在LDMOS 200只有沿着切线EE’的侧视图和LDMOS 100不同，所以另外以图5A绘示，其它侧示图如沿着切线FF’的侧视图和LDMOS 100沿着切线AA’的侧视图相同，请参阅图2A，而沿着切线GG’的侧视图和LDMOS 100沿着切线CC’的侧视图相同，请参阅图2C。
LDMOS 200的源极电极34同样包含一源极接触区34a和多个插栓34b，并且多个插栓34b和源极接触区34a相连，各个插栓34b延伸插入位于源极16位置的半导体基底10中，详细来说因为LDMOS 200没有金属硅化物阻挡层，因此各个插栓28b分别穿透金属硅化物24插入源极16，而源极接触区34a则是完全位于金属硅化物24上，也就是说金属硅化物24位于源极接触区34a和半导体基体10的上表面之间。
为了增加LDMOS晶体管元件线性区的漏极电流量，因而把基体设置在较浅处，但如此一来会使得半导体基底上累积电荷造成漏电流，然而本发明特意将部分的源极电极插入源极，并且延伸至接触基体的深度，如此可以避免漏电流。此外，因为源极电极只有数个插栓插入源极，所以线性区的漏极电流量不会因此降低。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种横向双扩散的金属氧化物半导体场效晶体管，其特征在于，包含：
半导体基底；
阱区，设置于该半导体基底中；
基体(body)区，设置于该阱区中；
第一栅极电极，设置于该半导体基底上；
源极电极，设置在该第一栅极电极的一侧，其中该源极电极包含源极接触区和多个插栓(via)，并且该多个插栓和该源极接触区相连，该多个插栓延伸插入该半导体基底中；以及
第一漏极电极，设置在该第一栅极电极相对该源极电极的另一侧。
2.如权利要求1所述的横向双扩散的金属氧化物半导体场效晶体管，其中该源极接触区完全设置在该半导体基底的上表面之上。
3.如权利要求1所述的横向双扩散的金属氧化物半导体场效晶体管，另包含：
第二栅极电极，设置于该半导体基底上，其中该源极电极位于该第二栅极电极和该第一栅极电极之间；以及
第二漏极电极，设置在该第二栅极电极相对该源极电极的另一侧。
4.如权利要求1所述的横向双扩散的金属氧化物半导体场效晶体管，其中该基体区的底面和该半导体基底的上表面之间具有第一深度，该阱区的底面和该半导体基底的上表面之间具有第二深度，该第二深度大于该第一深度。
5.如权利要求4所述的横向双扩散的金属氧化物半导体场效晶体管，其中各该插栓的末端和该半导体基底的上表面之间具有第三深度，该第三深度大于该第一深度。
6.如权利要求4所述的横向双扩散的金属氧化物半导体场效晶体管，其中各该插栓的末端和该半导体基底的上表面之间具有第三深度，该第三深度等于该第一深度。
7.如权利要求1所述的横向双扩散的金属氧化物半导体场效晶体管，另包含金属硅化物，设置在该源极接触区和该半导体基底的上表面之间。
8.如权利要求1所述的横向双扩散的金属氧化物半导体场效晶体管，其中该半导体基底为第一导电型态，该阱区为第二导电型态，该基体区为第一导电型态，该第一导电型态和该第二导电型态不同。
9.如权利要求8所述的横向双扩散的金属氧化物半导体场效晶体管，另包含多个掺杂区，分别位于各该插栓的下方的该阱区中，该多个掺杂区为第一导电型态。
10.一种横向双扩散的金属氧化物半导体场效晶体管的制作方法，包含：
提供半导体基底，其中阱区设置于该半导体基底中，基体(body)区设置于该阱区中，栅极电极设置于该半导体基底上，漏极和源极位于该栅极电极两侧的该半导体基底中；
形成金属硅化物阻挡层覆盖该源极，其中该金属硅化物阻挡层包含多个长条形轮廓；
形成介电层覆盖该半导体基底；
蚀刻该介电层和该金属硅化物阻挡层以形成源极接触洞位于该源极正上方，其中该源极接触洞包含沟槽和多个通孔，该多个通孔和该沟槽相连，该多个通孔穿透该金属硅化物阻挡层并且插入该源极，该沟槽只位于该介电层中；以及
形成导电层填入该源极接触洞，以形成源极电极。
11.如权利要求10所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中该源极电极包含源极接触区和多个插栓(via)和该源极接触区相连，各该插栓分别位于各该通孔中，该源极接触区位于该沟槽中。
12.如权利要求11所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中该基体区的底面和该半导体基底的上表面之间具有第一深度，该阱区的底面和该半导体基底的上表面之间具有第二深度，该第二深度大于该第一深度。
13.如权利要求12所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中各该插栓的末端和该半导体基底的上表面之间具有第三深度，该第三深度大于该第一深度。
14.如权利要求12所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中各该插栓的末端和该半导体基底的上表面之间具有第三深度，该第三深度等于该第一深度。
15.一种横向双扩散的金属氧化物半导体场效晶体管的制作方法，包含：
提供半导体基底，其中阱区设置于该半导体基底中，基体区设置于该阱区中，栅极电极设置于该半导体基底上，漏极及源极位于该栅极电极两侧的该半导体基底中；.
进行金属硅化制作工艺，形成金属硅化物覆盖该源极和该漏极；
形成介电层覆盖该栅极电极、该漏极及该源极；
进行第一蚀刻制作工艺，蚀刻该介电层、该金属硅化物以及该半导体基底以形成多个通孔穿透该金属硅化物并且插入该源极；
进行第二蚀刻制作工艺，蚀刻该介电层以形成沟槽在该源极的正上方的该介电层中，其中该沟槽和该多个通孔相连构成源极接触洞；以及
形成导电层填入该源极接触洞，以形成源极电极并且该源极电极和该金属硅化物相连接。
16.如权利要求15所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中该源极电极包含源极接触区和多个插栓(via)和该源极接触区相连，各该插栓分别位于各该通孔中，该源极接触区位于该沟槽中。
17.如权利要求16所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中该基体区的底面和该半导体基底的上表面之间具有第一深度，该阱区的底面和该半导体基底的上表面之间具有第二深度，该第二深度大于该第一深度。
18.如权利要求17所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中各该插栓的末端和该半导体基底的上表面之间具有第三深度，该第三深度大于该第一深度。
19.如权利要求17所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，其中各该插栓的末端和该半导体基底的上表面之间具有第三深度，该第三深度等于该第一深度。
20.如权利要求17所述的横向双扩散的金属氧化物半导体场效晶体管的制作方法，另包含在形该多个通孔后，形成多个掺杂区分别位于各该通孔的下方。
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