TW499757B - High voltage power MOSEFT having low on-resistance - Google Patents

High voltage power MOSEFT having low on-resistance Download PDF

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TW499757B
TW499757B TW090113258A TW90113258A TW499757B TW 499757 B TW499757 B TW 499757B TW 090113258 A TW090113258 A TW 090113258A TW 90113258 A TW90113258 A TW 90113258A TW 499757 B TW499757 B TW 499757B
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Richard A Blanchard
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Gen Semiconductor Inc
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

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Abstract

A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Description

499757 A7 _·_ B7_ 五、發明説明（1 ) 相關申請案： 此申請案係有關美國臨時專利申請案序列第 (請先閱讀背面之注意事項再填寫本頁) 60/137 ，408號案（提申於1999年6月3日 ’標題爲、、A High Voltage MOS-Gated Structure with a Relatively Low On-Resistance” ）。 本發明之領域： 本發明係有關一般的半導體裝置，尤指功率 M0SFET裝置。 本發明之背景： 功率Μ 0 S F E T裝置被使用於諸應用中，例如汽車 電氣系統、電源供應器及電力管理應用等等。這樣的裝置 在關閉狀態中應該維持高電壓，並且在開啓狀態中應該產 生低電壓及高飽和電流密度。 經濟部智慧財產局員工消費合作社印製 圖1例舉一 Ν通道功率Μ〇S F Ε Τ之典型結構。一 被形成在Ν +矽基體2上之Ν -磊晶矽層1包含用於此裝 置中之兩M0SFET單元的ρ —體區5a ，6a和Ν + 源極區7及8，P -體區5及6也可以包含深P —體區5 b及6 b ，一源極一體電極1 2延伸跨越磊晶層1的某些 表面部分，以接觸源極及體區域。藉由延伸至圖1中之上 半導體表面的N -磊晶層1部分來形成兩單元之N型汲極 ，一汲極電極（未被單獨顯示出）被設置於N +基體2的 底部，一包括氧化物及多晶矽層之絕緣閘極電極1 8覆於 -4 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 499757 A7 B7 五、發明説明（2 ) 此體的通道及汲極部分之上。 (請先閱讀背面之注意事項再填寫本頁) 圖1中所示之習知M〇S F E T的接通電阻主要係由 磊晶層1之漂移區電阻所決定的，漂移區電阻同樣也由摻 雜及磊晶層1之層厚度所決定的。但是，爲了增加裝置的 崩潰電壓，必須降低磊晶層1的摻雜濃度，而同時增加層 厚度。圖2中之曲線2 0顯示每單位面積之接通電阻，作 爲習知Μ 0 S F E T之崩潰電壓的函數，不幸地，如曲線 2 0顯示，裝置之接通電阻隨著其崩潰電壓的增加而快速 地增加，此電阻方面的快速增加顯現了當Μ 0 S F Ε Τ即 將被操作於較高電壓，特別是操作於大於幾百伏特之電壓 的問題。 經濟部智慧財產局員工消費合作社印製 圖3顯示被設計操作於較高電壓，具有降低之接通電 阻的Μ〇S F Ε Τ，此Μ〇S F Ε Τ被揭示於Γ E D Μ年 報，1998年，第683頁之第26·2篇論文中，此 M〇S F Ε Τ與圖2中所示之習知MO S F Ε Τ相類似， 除了其包含Ρ型摻雜區4 0及4 2以外，而ρ型摻雜區自 體區域5及6的底下延伸至裝置的漂移區中，Ρ型摻雜區 4 0及4 2產生反向電壓，此反向電壓不僅即將被建立於 垂直方向（如同在習知MO S F Ε Τ中）上，而且也即將 被建立於水平方向上，結果’此裝置能夠獲得和習知裝置 相同的反向電壓，此習知裝置具有磊晶層1之所減少的層 厚度及具有漂移區中之所增加的摻雜濃度。圖2中之曲線 2 5顯示每單位面積之接通電阻，作爲圖3中所示之 Μ〇S F Ε Τ之崩潰電壓的函數，很淸楚地，在較高的操 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -5- 499757 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（3 ) 作電壓處’此裝置之接通電阻相對於圖1中所示之裝置實 際上被減少，基本上隨著崩潰電壓而線性地增加。 圖3中所示之結構能夠用一包含多個磊晶沉積步驟之 程序序列來予以製造，各步驟繼之以適當摻雜劑的引進。 不幸地’磊晶沉積步驟之實施所費不貲，而因此，此結構 之製造係昂貴的。 如上所述，提供一種製造圖3中所示之M〇S F ET 結構的方法係令人滿意的，其需要最小數目的沉積步驟， 使得他能夠被便宜地製造。 本發明之槪述： 根據本發明，提供一種功率MO S F E T，其包含一 爲第一導電類型的基體，也是第一導電類型之磊晶層被沉 積於此基體上，第一及第二體區域係位在磊晶層中，並界 定他們之間的漂移區，體區域具有第二導電類型，第一導 電類型之第一及第二源極區分別位在第一及第二體區域中 ，多個溝槽係位在磊晶層之漂移區中之體區域的下方，從 第一及第二體區域延伸向基體之溝槽被塡充以磊晶層材料 ，其包含一第二導電類型的摻雜劑，摻雜劑自溝槽而被擴 散至鄰接溝槽之磊晶層的部分中，因此形成了 p型摻雜區 ，其造成了即將被建立於水平方向以及垂直方向上的反向 電壓。 根據本發明之其中一觀點，塡充溝槽之材料爲多晶矽 (請先閱讀背面之注意事項再填寫本頁) 衣.499757 A7 _ · _ B7_ V. Description of the invention (1) Related applications: This application is related to the US provisional patent application sequence number (Please read the precautions on the back before filling this page) No. 60/137, 408 ( Submitted on June 3, 1999, with the title, "A High Voltage MOS-Gated Structure with a Relatively Low On-Resistance"). Field of the Invention: The present invention relates to general semiconductor devices, especially power MOSFET devices. Background of the invention: Power M 0 SFET devices are used in applications such as automotive electrical systems, power supplies and power management applications, etc. Such devices should maintain high voltages in the off state and in the on state Low voltage and high saturation current density should be generated. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy, Figure 1 illustrates a typical structure of the N channel power MOSF ET. One is formed on the N + silicon substrate 2- The epitaxial silicon layer 1 includes p-body regions 5a, 6a and N + source regions 7 and 8 for two MOSFET cells in this device. P-body regions 5 and 6 may also include deep P-body regions 5b. And 6 b A source integrated electrode 12 extends across some surface portions of the epitaxial layer 1 to contact the source and body regions. Two portions are formed by extending to the N-epitaxial layer 1 portion of the semiconductor surface above FIG. 1. The unit's N-type drain electrode, a drain electrode (not shown separately) is arranged at the bottom of the N + substrate 2, an insulating gate electrode including an oxide and a polycrystalline silicon layer 1 8 covers -4-this paper standard Applicable to China National Standard (CNS) A4 specification (210X297 mm) 499757 A7 B7 V. Description of invention (2) Above the channel and drain part of this body (Please read the precautions on the back before filling this page) Figure 1 The on-resistance of the conventional MOSFET shown in the figure is mainly determined by the drift region resistance of the epitaxial layer 1. The drift region resistance is also determined by the doping and the layer thickness of the epitaxial layer 1. However, In order to increase the breakdown voltage of the device, it is necessary to reduce the doping concentration of the epitaxial layer 1 while increasing the layer thickness. The curve 20 in FIG. 2 shows the on-resistance per unit area as the breakdown voltage of the conventional M 0 SFET. Function, unfortunately, as curve 2 0 shows, the device The on-resistance increases rapidly as its breakdown voltage increases. This rapid increase in resistance shows the problem when M 0 SF ΕΤ is about to be operated at higher voltages, especially at voltages greater than a few hundred volts. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, Figure 3 shows the MOSF ET designed to operate at higher voltages with reduced on-resistance. This MOSF ET is disclosed in the Γ ED Μ annual report, 1998 In the 26.2 paper on page 683, this MoSF ET is similar to the conventional MO SF ET shown in FIG. 2 except that it contains P-type doped regions 40 and 42. The p-type doped regions extend from the bottom of the body regions 5 and 6 into the drift region of the device. The p-type doped regions 40 and 42 generate reverse voltages. This reverse voltage will not only be established in the vertical direction (like In the conventional MO SF ET), and it is about to be established in the horizontal direction, the result 'this device can obtain the same reverse voltage as the conventional device, this conventional device has the reduced epitaxial layer 1 Layer thickness and increased doping concentration in drift regions . The curve 25 in Fig. 2 shows the on-resistance per unit area as a function of the breakdown voltage of MOSF ET shown in Fig. 3, and it is clear that it is suitable for the Chinese country at a higher operating paper size. Standard (CNS) A4 specification (210 × 297 mm) -5- 499757 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (3) The voltage at which the on-resistance of this device is relative to that shown in Figure 1. The device shown is actually reduced, increasing substantially linearly with the breakdown voltage. The structure shown in Fig. 3 can be fabricated using a sequence of processes including multiple epitaxial deposition steps, each step being followed by the introduction of a suitable dopant. Unfortunately, the implementation of the 'epitaxial deposition step is expensive, and therefore, the fabrication of this structure is expensive. As described above, it is satisfactory to provide a method for manufacturing the MOS F ET structure shown in FIG. 3, which requires a minimum number of deposition steps so that it can be manufactured inexpensively. Description of the present invention: According to the present invention, a power MO SFET is provided, which comprises a substrate of a first conductivity type, and an epitaxial layer of the first conductivity type is deposited on the substrate, and the first and second body regions It is located in the epitaxial layer and defines a drift region between them. The body region has a second conductivity type. The first and second source regions of the first conductivity type are located in the first and second body regions. The plurality of trenches are located below the body region in the drift region of the epitaxial layer, and the trenches extending from the first and second body regions to the substrate are filled with the epitaxial layer material, which includes a second conductivity type Dopant, the dopant is diffused from the trench to the portion of the epitaxial layer adjacent to the trench, so a p-type doped region is formed, which causes the anti-reflections to be established in the horizontal and vertical directions向 volt. According to one aspect of the present invention, the material of the filling groove is polycrystalline silicon (please read the precautions on the back before filling this page).

、1T 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨Ο X 297公釐） -6 - 499757 Α7 Β7 五、發明説明（4 ) 根據本發明之另一觀點，塡充溝槽之多晶矽係至少被 局部氧化。或者多晶矽可以隨後被再結晶以形成單結晶矽 〇 根據本發明之又一觀點，塡充溝槽之.材料爲舉例來說 諸如二氧化矽之電介質。 根據本發明之再一觀點，塡充溝槽之材料可以包含矽 及電介質兩者。 根據本發明之仍一觀點，提供一種用以形成功率 M〇S F E T之方法，此方法藉由提供一爲第一導電類型 的基體’並且將一磊晶層沉積於此基體之上而開始，磊晶 層具有第一導電類型，第一及第二體區域被形成在磊晶層 中，以界定介於其間之漂移區，體區域具有第二導電類型 ，第一導電類型之第一及第二源極區分別被形成在第一及 第二體區域中，多個溝槽被形成在磊晶層的漂移區中，以 具有第二導電類型之摻雜劑的材料塡充溝槽，溝槽從第一 及第二體區域延伸向基體，至少一部分的摻雜劑從溝槽被 擴散至鄰接溝槽之磊晶層的部分中。 附圖之簡略說明： 圖1顯示習知功率Μ〇S F E T的剖面圖。 ^ 圖2顯示每單位面積之接通電阻，其作爲習知功率 M〇S F ΕΤ及根據本發明所建構之M〇S F ΕΤ之崩潰 電壓的函數。 圖3顯示被設計來以每單位面積具有比圖1所描述之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 、1Τ 經濟部智慧財產局員工消費合作社印製 499757 A7 __________ _B7 五、發明説明（5 ) 結構還低的接通電阻，操作於相同電壓的Μ〇S F E T結 構。 圖4至圖6顯示根據本發明所建構之功率 Μ〇S F Ε Τ的各種實施例之有關係的部分。 圖7顯示根據本發明所建構之完成的功率 Μ 〇 S F Ε Τ 。 元件對照表 1 嘉晶層 2 Ν +矽基體 5，6 Ρ -體區 5a，6a ρ —體區 5b，6b 深ρ —體區 7，8 Ν +源極區 1 2 源極一體電極 40，42 Ρ型摻雜區 4 4，4 6 溝槽 48 氧化物層 4 9 多晶矽層 5 0 金屬化層 18 絕緣閘極電極 較佳實施例之詳細說明： 根據本發明，圖3所示之ρ型區4 0及4 2之形成係 本紙张尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 f 經濟部智慧財產局員工消費合作社印製 -8- 499757 A7 B7_ 五、發明説明（6 ) (請先閱讀背面之注意事項再填寫本頁) 藉由首先蝕刻一對以p型區4 0及4 2即將被定位之位置 爲中心的溝槽，溝槽隨後被塡充以富有摻雜劑之材料，材 料中的摻雜劑被擴散到溝槽之外，並擴散進入形成裝置之 漂移區之鄰近的磊晶層，磊晶層的最終摻雜部分形成p型 區，塡充溝槽之材料以及未被擴散到溝槽之外的摻雜劑依 然在最終裝置中。因此，應該選擇材料，使其對裝置之特 性不會有不利的影響，可以被使用作塡充溝槽之材料的代 表性材料包含多晶矽或諸如二氧化矽之電介質。 圖4至圖6顯示可以被使用來塡充被形成於磊晶矽層 1中之溝槽4 4及4 6之材料的幾種不同組合，在圖4至 圖6顯示溝槽4 4及4 6、磊晶層1、及基體2的同時， 爲了淸楚起見，圖4至圖6並不顯示功率MO S F ET結 構之上層部分，其包含P -體區及源極。 在圖4中，溝槽4 4及4 6被塡充以摻雜電介質，例 如摻硼之二氧化矽。在溝槽被塡充之後，硼被擴散入相鄰 之磊晶層1中以形成p型區4 0及4 2，塡充溝槽之摻硼 的二氧化矽依然在最終的Μ〇S F E T裝置中。 經濟部智慧財產局員工消費合作社印製 在圖5中’溝槽至少局部被塡充以摻雜有硼之多晶系 矽（例如多晶矽）’在溝槽被塡充之後，硼被擴散入相鄰 之晶晶層1中以形成Ρ型區4 0及4 2，剩下的塡充溝槽 之摻硼的二氧化矽依然在最終的Μ〇S F Ε Τ裝置中。或 者在擴散被實施之後，多晶矽通通或局部被氧化以形成二 氧化砂。因此’依然在最終之Μ 0 S F Ε Τ裝置中的溝槽 被塡充以電介質（例如二氧化矽）以及任何殘留的多晶矽 本紙張尺度適用中國國家標準（CNS ) A4規格0X297公釐） 一 -9- 499757 A 7 B7 五、發明説明（7 ) (請先閱讀背面之注意事項再填寫本頁) 。在另一選擇情況中，溝槽中任何的摻硼之多晶政被再結 晶於上升溫度時，以形成單結晶矽。在此情況中，依然在 最終之Μ〇S F E T裝置中的溝槽被塡充以單結晶矽，或 者單結晶矽結合二氧化矽，或另一電介質。 在圖6中，溝槽4 4及4 6首先被局部塡充以摻雜之 多晶矽，繼之以電介質的沉積，以完全塡充溝槽。在溝槽 被塡充之後，硼被擴散入枏鄰之磊晶層1中以形成ρ型區 4 0及4 2，剩餘之摻硼的多晶矽及塡充溝槽之電介質依 然在最終的Μ 0 S F Ε Τ裝置中。在某些情況中，摻硼的 多晶矽被再結晶於上升溫度時，以形成單結晶矽。因此， 依然在最終之Μ 0 S F Ε Τ裝置中的溝槽被塡充以單結晶 矽及電介質二者。 經濟部智慧財產局員工消費合作社印製 圖7顯示根據本發明所建構之最終的功率 MOSFET，此MOSFET包含基體2、磊晶層1 、 Ρ -體區5 a及6 a、深ρ —體區5b及6b、源極區7 及8、及ρ型區40及42 (而溝槽44及46分別被配 置於其中），P型區4 0及4 2界定柱狀物，各柱狀物被 η型摻雜之柱狀物所分開。閘極電極及源極-體電極也被 顯示出，閘極電極包含氧化物層4 8及多晶矽層4 9，而 源極-體電極包含金屬化層5 0。 可以根據任何習知處理技術來製造圖7所示之發明的 功率Μ 0 S F Ε Τ，舉例來說，可以實施以下序列的代表 性步驟來形成圖7所描述之功率Μ 0 S F Ε Τ。 首先，藉由以一層氧化物層覆蓋磊晶層1之表面來形 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 499757 A7 ___B7 _ 五、發明説明（8 ) (請先閱讀背面之注意事項再填寫本頁) 成氧化物遮罩層，然後傳統上被曝光及圖案化而留下界定 溝槽4 4及4 6之位置的遮罩部分，溝槽藉由反應離子蝕 刻法而經由遮罩開口被乾式鈾刻至一深度，而典型上深度 範圍從1 0到4 0微米，可以使各溝槽的側壁平滑。首先 ，乾式化學蝕刻可以被用來自溝槽側壁去除薄的氧化物層 (典型上約5 0 0 — 1 0 0 0 A )，以消除由反應離子蝕 刻程序所造成的損壞，接著，在溝槽4 4及4 6和遮罩部 分上長出一層犧牲的二氧化矽層，藉由一緩衝氧化物蝕刻 或一 H F蝕刻來去除犧牲層及遮罩部分，使得最終的溝槽 側壁爲盡可能地平滑。 以任何先前所述的材料（例如多晶矽、二氧化矽、矽 、或其組合）來塡充溝槽4 4及4 6，在沉積期間，多晶 矽或氧化物典型上被摻雜有例如硼之摻雜劑。後續的擴散 步驟被實施以使摻雜劑擴散到溝槽之外，及擴散入環繞的 磊晶層中，如果殘餘在溝槽中之材料爲多晶矽，則其可以 被氧化或再結晶化。 經濟部智慧財產局員工消費合作社印製 接著，Ν摻雜磊晶層1被生長在習知Ν +摻雜基體2 上，對具有1 5 — 6 0歐姆—cm之電阻率的4 0 0 — 8 0 0V裝置來說，磊晶層1典型上厚度爲1 5 — 5 0微 米。在一活性區遮罩及一層多晶系矽被沉積、摻雜及氧化 之後，閘極氧化物接著被生長，如果被使用的話，使用習 知遮罩、離子植入及擴散程序來形成深P -體區5 b及6 b，深p -體區的劑量典型上範圍從約1 X 1 0 1 4到5 X 1 0 1 5 / c m 2。接著，p —體區5 a及6 a被形成於習 本紙張尺度適用中周國家標準（CNS ) A4規格（210Χ297公釐） - 11 - 經濟部智慧財產局員工消費合作社印製 499757 A7 ^___B7 五、發明説明（9 ) 知遮罩、植入及擴散步驟中，在4 〇到6 0 K e V時，以 劑量從約1 X 1 0 1 3到5 X 1 〇 1 4 / c m 2來植入硼於 p —體區中。 接著，光阻遮罩程序被用來形成一界定源極區7及8 之經圖案化的遮罩層’源極區7及8然後藉由植入及擴散 程序而被形成，舉例來說，源極區可以用8 0 K e V而以 砷來植入至典型上在2x 1 015到1 . 2x 1 016/ c m 2的範圍中之濃度。在植入之後，砷被擴散至約〇 . 5 到2 . 0微米的深度，深p -體區的深度典型上範圍從 2 · 5到5微米，而體區的深度在深度上範圍從約1到3 微米。最後，按照習知的方式去除遮罩層，以形成圖7所 描述之結構。 按照習知的方式，藉由形成及圖案化氧化物層來形成 接點開口，以完成D Μ〇S電晶體。一金屬化層5 0也被 沉積及遮罩，以界定源極-體電極及閘極電極。又，一墊 塊（p a d )遮罩被用來界定一墊塊（p a d )接點，最 後，一汲極接觸層（未顯示出）被形成在基體的底面上。 應該注意到，在先前所述的程序中，溝槽在P -體區 及深p -體區的形成之前先被形成，本發明更一般包含溝 槽被形成在任何或所有剩餘的摻雜區之前或之後的程序。 除此之外，在用以製造功率M 0 s F E τ之特定製程序列 被揭示其他的同時，其他的製程序列可以被使用而依然在 本發明的範疇之內。 根據本發明所建構之功率Μ 〇 S F Ε Τ·提供許多優於 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)、 1T This paper size is in accordance with Chinese National Standard (CNS) A4 specification (2 丨 〇 X 297 mm) -6-499757 Α7 Β7 5. Description of the invention (4) According to another aspect of the present invention, the polycrystalline silicon filled with trenches The system is at least partially oxidized. Alternatively, polycrystalline silicon can be subsequently recrystallized to form single crystalline silicon. According to yet another aspect of the present invention, the material for filling the trench is, for example, a dielectric such as silicon dioxide. According to still another aspect of the present invention, the material of the filling trench may include both silicon and dielectric. According to still another aspect of the present invention, a method for forming a power MOSFET is provided. This method begins by providing a substrate of a first conductivity type and depositing an epitaxial layer on the substrate. The crystal layer has a first conductivity type, and first and second body regions are formed in the epitaxial layer to define a drift region therebetween. The body region has a second conductivity type, and the first and second conductivity types are first and second. The source region is formed in the first and second body regions, respectively. A plurality of trenches are formed in the drift region of the epitaxial layer. The trenches are filled with a material having a second conductivity type dopant. Extending from the first and second body regions to the substrate, at least a portion of the dopant is diffused from the trench into a portion of the epitaxial layer adjacent to the trench. Brief description of the drawings: FIG. 1 shows a cross-sectional view of a conventional power MOS FET. ^ Figure 2 shows the on-resistance per unit area as a function of the breakdown voltage of the conventional power MOS F ET and the MOS F ET constructed according to the present invention. Figure 3 shows that the paper size is designed to apply the Chinese National Standard (CNS) A4 specification (210 × 297 mm) per unit area than the paper size described in Figure 1. (Please read the precautions on the back before filling this page), 1T Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau 499757 A7 __________ _B7 V. Description of the invention (5) The structure has a low on-resistance and operates at the same voltage MOSFET structure. Figures 4 to 6 show the relevant parts of various embodiments of the power MOS F ET constructed in accordance with the present invention. FIG. 7 shows the completed power MOS F ET constructed in accordance with the present invention. Element comparison table 1 Jiajing layer 2 N + silicon substrate 5, 6 P-body region 5a, 6a ρ-body region 5b, 6b deep ρ-body region 7, 8 Ν + source region 1 2 source integrated electrode 40, 42 P-type doped region 4 4, 4 6 trench 48 oxide layer 4 9 polycrystalline silicon layer 5 0 metallization layer 18 detailed description of a preferred embodiment of an insulated gate electrode: According to the present invention, the p-type shown in FIG. 3 The formation of zones 40 and 4 2 is based on the Chinese paper standard (CNS) A4 (210X297 mm). (Please read the precautions on the back before filling this page.) System-8- 499757 A7 B7_ V. Description of the invention (6) (Please read the precautions on the back before filling this page) By first etching a pair of p-type regions 4 0 and 4 2 to be positioned as the center The trench is then filled with a dopant-rich material, and the dopant in the material is diffused out of the trench and diffuses into the adjacent epitaxial layer forming the drift region of the device. The final doped portion forms a p-type region, filling the trench material and doping that has not diffused outside the trench However, in accordance with the final device. Therefore, the material should be selected so that it does not adversely affect the characteristics of the device. Representative materials that can be used as the material for the filling trench include polycrystalline silicon or a dielectric such as silicon dioxide. Figures 4 to 6 show several different combinations of materials that can be used to fill the trenches 4 4 and 4 6 formed in the epitaxial silicon layer 1. Figures 4 to 6 show the trenches 4 4 and 4 6. At the same time as the epitaxial layer 1, and the substrate 2, for the sake of clarity, FIGS. 4 to 6 do not show the upper part of the power MO SF ET structure, which includes the P-body region and the source. In Figure 4, the trenches 44 and 46 are filled with a doped dielectric, such as boron-doped silicon dioxide. After the trench is fully charged, boron is diffused into the adjacent epitaxial layer 1 to form p-type regions 40 and 42. The boron-doped silicon dioxide in the filled trench is still in the final MOSFET device. in. Printed in Figure 5 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, “The trench is at least partially filled with polycrystalline silicon (eg, polycrystalline silicon) doped with boron”. After the trench is filled, boron is diffused into the phase. Neighboring crystal layer 1 forms P-type regions 40 and 42, and the remaining boron-doped silicon dioxide in the still-filled trench is still in the final MOSF ET device. Or, after the diffusion is performed, the polycrystalline silicon is partially or partially oxidized to form sand dioxide. Therefore, the trenches still in the final M 0 SF ET device are filled with a dielectric (such as silicon dioxide) and any remaining polycrystalline silicon. The paper size is applicable to the Chinese National Standard (CNS) A4 specification 0X297 mm)- 9- 499757 A 7 B7 V. Description of the invention (7) (Please read the notes on the back before filling this page). In another alternative, any boron-doped polycrystalline silicon in the trench is recrystallized at an elevated temperature to form a single crystalline silicon. In this case, the trenches still in the final MOS FET device are filled with single crystal silicon, or single crystal silicon combined with silicon dioxide, or another dielectric. In Fig. 6, the trenches 44 and 46 are first partially filled with doped polycrystalline silicon, followed by dielectric deposition to completely fill the trenches. After the trench is filled, boron is diffused into the adjacent epitaxial layer 1 to form p-type regions 40 and 42. The remaining boron-doped polycrystalline silicon and the dielectric of the filled trench are still at the final M 0 SF Ε Τ device. In some cases, boron-doped polycrystalline silicon is recrystallized at elevated temperatures to form single crystalline silicon. Therefore, the trenches still in the final MOSFET device are filled with both single crystal silicon and dielectric. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 7 shows the final power MOSFET constructed according to the present invention. The MOSFET includes a base body 2, an epitaxial layer 1, p-body regions 5a and 6a, and a deep p-body region. 5b and 6b, source regions 7 and 8, and p-type regions 40 and 42 (while trenches 44 and 46 are arranged therein), P-type regions 40 and 42 define pillars, and each pillar is The n-type doped pillars are separated. The gate electrode and the source-body electrode are also shown. The gate electrode includes an oxide layer 48 and a polycrystalline silicon layer 49, and the source-body electrode includes a metallization layer 50. The power M 0 S F E T of the invention shown in FIG. 7 can be manufactured according to any conventional processing technology. For example, the representative sequence of the following sequence can be implemented to form the power M 0 S F E T described in FIG. 7. First, by covering the surface of epitaxial layer 1 with an oxide layer, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 499757 A7 ___B7 _ V. Description of the invention (8) (Please read first Note on the back, please fill in this page again) to form an oxide mask layer, and then it is traditionally exposed and patterned to leave the mask portion defining the positions of the trenches 4 4 and 46. The trenches are formed by reactive ion etching. The dry uranium is etched to a depth through the mask opening, and the typical depth range is from 10 to 40 microns, which can make the sidewalls of each trench smooth. First, a dry chemical etch can be used to remove a thin oxide layer (typically about 500-100 A) from the sidewalls of the trench to eliminate damage caused by the reactive ion etching process. A sacrificial silicon dioxide layer is grown on the 4 4 and 4 6 and the mask portion. The sacrificial layer and the mask portion are removed by a buffer oxide etching or an HF etching, so that the final trench sidewall is as much as possible. smooth. The trenches 4 4 and 4 6 are filled with any of the previously described materials (eg, polycrystalline silicon, silicon dioxide, silicon, or a combination thereof). During deposition, the polycrystalline silicon or oxide is typically doped with a dopant such as boron. Miscellaneous. Subsequent diffusion steps are performed to diffuse the dopants out of the trench and into the surrounding epitaxial layer. If the material remaining in the trench is polycrystalline silicon, it can be oxidized or recrystallized. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, the N-doped epitaxial layer 1 is grown on the conventional N + -doped substrate 2 to 4 0 — with a resistivity of 1 5-6 0 ohm-cm. For 800V devices, the epitaxial layer 1 typically has a thickness of 15-50 microns. After an active area mask and a layer of polycrystalline silicon are deposited, doped, and oxidized, the gate oxide is then grown. If used, deep masks are formed using conventional masking, ion implantation, and diffusion procedures. -Body zone 5 b and 6 b, deep p -Dose of body zone typically ranges from about 1 X 1 0 1 4 to 5 X 1 0 1 5 / cm 2. Next, the p-body regions 5 a and 6 a were formed on the paper scale of the book to apply the Mid-week National Standard (CNS) A4 specification (210 × 297 mm). V. Description of the invention (9) In the step of masking, implantation and diffusion, the dose is from about 1 X 1 0 1 3 to 5 X 1 〇1 4 / cm 2 at 40 to 60 K e V. Boron is implanted in the p-body region. The photoresist masking procedure is then used to form a patterned masking layer defining source regions 7 and 8 and the source regions 7 and 8 are then formed by implantation and diffusion procedures, for example, The source region can be implanted with 80 KeV and arsenic to a concentration typically in the range of 2x1 015 to 1.2x1 016 / cm 2. After implantation, arsenic is diffused to a depth of about 0.5 to 2.0 micrometers, and the depth of the deep p-body region typically ranges from 2.5 to 5 micrometers, while the depth of the body region ranges in depth from about 1 to 3 microns. Finally, the mask layer is removed in a conventional manner to form the structure described in FIG. In a conventional manner, a contact opening is formed by forming and patterning an oxide layer to complete a DMOS transistor. A metallization layer 50 is also deposited and masked to define a source-body electrode and a gate electrode. In addition, a pad mask is used to define a pad contact. Finally, a drain contact layer (not shown) is formed on the bottom surface of the substrate. It should be noted that in the previously described procedure, the trenches are formed before the formation of the P-body region and the deep p-body region, and the present invention more generally encompasses that the trenches are formed in any or all remaining doped regions Before or after the procedure. In addition, while the specific manufacturing process sequence used to make the power M 0 s F E τ is disclosed, other manufacturing process sequences can be used while remaining within the scope of the present invention. The power MOS F ET constructed according to the present invention provides many advantages over the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

499757 A7 B7 五、發明説明（1〇) 由習知技術所建構之習知裝置的優點，舉例來說，P型區 的垂直摻雜劑梯度非常接近零，水平摻雜劑梯度可以藉由 改變被引進之摻雜劑的量及在擴散步驟中所使用之熱循環 的數目及期間來予以正確地控制。此外，所引進之摻雜劑 的量及橫向摻雜劑梯度能夠被改變，以使裝置之崩潰電壓 及接通電阻最佳化。 在圖7所示之本發明的實施例中，p型溝槽被形成在 體區域的下方。但是，並不是每一個P型溝槽需要具有與 其相關聯的體區域，特別是在晶片的周邊或在含有墊塊或 互連之區域中。 雖然各種實施例被特定例舉及說明於此，將可領會本 發明的修正及改變可以被上述教旨所涵蓋，並且是在所附 加之申請專利項的範圍之內，但沒有違反本發明的精神及 範疇，舉例來說，根據本發明之功率Μ〇S F E T可以被 設置，其中各個半導體區的導電性與在此所述之導電性相 反0 (請先聞讀背面之注意事¾再填寫本頁) •夢 -訂 .— 經濟部智慧財產局員工消費合作社印製 一適 ΐ 尺 一張 紙 準 標 家 |釐 公 7 9 2499757 A7 B7 V. Description of the invention (10) The advantages of the conventional device constructed by conventional technology. For example, the vertical dopant gradient of the P-type region is very close to zero, and the horizontal dopant gradient can be changed by The amount of dopant introduced and the number and duration of thermal cycles used in the diffusion step are properly controlled. In addition, the amount of dopant introduced and the lateral dopant gradient can be changed to optimize the breakdown voltage and on-resistance of the device. In the embodiment of the present invention shown in Fig. 7, a p-type groove is formed below the body region. However, not every P-type trench needs to have a body region associated with it, especially at the periphery of the wafer or in areas containing pads or interconnects. Although various embodiments are specifically exemplified and described here, it will be appreciated that the amendments and changes of the present invention can be covered by the above teachings and are within the scope of the attached patent applications, but there is no violation of the present invention. The spirit and scope, for example, the power MOSFET according to the present invention can be set, in which the conductivity of each semiconductor region is opposite to that described herein. 0 (Please read the notes on the back ¾ before filling this Page) • Dream-Order. — The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a suitable ruler, a piece of paper, a standard bidder | Cong 7 9 2

Claims (1)

499757 A8 B8 C8 D8 六、申請專利範圍 彳 1 · 一種功率MOSFET，其包含·· 一第一導電類型的基體； (請先聞讀背面之注意事項再填寫本頁) 一基體上之磊晶層，該磊晶層具有第一導電類型； 第一及第二體區域，位在界定其間之漂移區的磊晶層 中，該等體區域具有第二導電類型； 第一導電類型之第一及第二源極區，分別位在第一及 第二體區域中；以及 多個溝槽，位在磊晶層之該漂移區中之該等體區域的 下方，該等溝槽被塡充以具有第二導電類型之摻雜劑的磊 晶層材料，該等溝槽從第一及第二體區域延伸向基體，該 摻雜劑自該等溝槽而被擴散至鄰接溝槽之磊晶層的部分中 〇 2 ·如申請專利範圍第1項之功率Μ〇S F E T，其 中塡充溝槽之該材料爲多晶矽。 3 .如申請專利範圍第1項之功率Μ 0 S F Ε Τ，其 中塡充溝槽之該材料爲電介質。 4 ·如申請專利範圔第3項之功率Μ 0 S F Ε Τ，其 經濟部智慧財產局員工消費合作社印製 中該電介質爲二氧化矽。 5 ·如申請專利範圍第1項之功率Μ 0 S F Ε Τ，其 中該摻雜劑爲硼。 6 .如申請專利範圍第2項之功率Μ〇S F Ε Τ，其 中該多晶砍係至少被局部氧化。 7 .如申請專利範圍第2項之功率Μ〇S F Ε Τ，其 中該多晶矽隨後被再結晶以形成單結晶矽。 本紙張尺度適用中國國家標準( CNS ) Α4規格（210X 297公釐) ' ~ -14- 499757 A8 B8 C8 D8 六、申請專利範圍 2 經濟部智慧財產局員工消費合作社印製 8 .如申請專利範圍第1項之功率Μ〇S F E T，其 中塡充溝槽之該材料包含多晶矽及電介質。 9 ·如申請專利範圍第1項之功率Μ 0 S F Ε Τ，其 中該等體區域包含深體區域。 1 0 ·如申請專利範圍第6項之功率Μ〇S F Ε Τ， 其中該多晶矽隨後被再結晶以形成單結晶矽。 11·一種形成功率MOSFET之方法，其包含步 驟： 提供一第一導電類型的基體； 沉積一磊晶層於基體上，該磊晶層具有第一導電類型 9 形成第一及第二體區域於嘉晶層中，以界定漂移區於 其間，該等體區域具有第二導電類型； 分別形成第一導電類型之第一及第二源極區於第一及 第二體區域中； 形成多個溝槽於磊晶層之該漂移區中； 以一具有第二導電類型之摻雜劑的材紐 μ *4纟興充該等溝槽 ，該等溝槽從第一及第二體區域延伸向基II ; ’以及 從該等溝槽中擴散至少一部分的該換W U雜劑至鄰接溝槽 之磊晶層的部分中。 1 2 .如申請專利範圍第1 1項之方 __ 法’其中塡充溝 槽之該材料包含多晶矽。 1 3 ·如申請專利範圍第1 1項之方g 槽之該材料爲電介質。 其中塡充溝 -----__^-IΦ II 寒 (請先閱讀背面之注意事項再填寫本頁) 、1T 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15、 經濟部智慧財產局員工消費合作社印製 499757 A8 B8 C8 P8 ____ 六、申請專利範圍 3 1 4 ·如申請專利範圍第1 3項之方法，其中該電介 質爲二氧化矽。 1 5 ·如申請專利範圍第1 1項之方法’其中該慘雜 劑爲硼。 1 6 ·如申請專利範圍第1 2項之方法’另包括至少 局部氧化該多晶矽之步驟。 1 7 ·如申請專利範圍第1 2項之方法’另包括使該 多晶矽再結晶以形成單結晶矽之步驟° 1 8 ·如申請專利範圍第1 1項之方法’其中塡充溝 槽之該材料包含多晶矽及電介質。 1 9 .如申請專利範圍第1 1項之方法，其中該等體 區域包含深體區域。 2 〇 .如申請專利範圍第1 1項之方法，其中該溝槽 之形成係藉由提供一界定至少其中一溝槽之遮罩層，並蝕 刻由該遮罩層所界定之溝槽。 2 1 .如申請專利範圍第1 1項之方法，其中該等體 區域係藉由將摻雜劑植入及擴散入基體中而予以形成。 2 2 ·如申請專利範圍第1 6項之方法，另包括使該 多晶矽再結晶以形成單結晶矽之步驟。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁)499757 A8 B8 C8 D8 6. Scope of patent application 彳 1. A power MOSFET, which includes a substrate of the first conductivity type; (Please read the precautions on the back before filling this page) An epitaxial layer on the substrate The epitaxial layer has a first conductivity type; the first and second body regions are located in the epitaxial layer defining a drift region therebetween; the bulk regions have a second conductivity type; the first and A second source region is respectively located in the first and second body regions; and a plurality of trenches are located below the body regions in the drift region of the epitaxial layer, and the trenches are filled with An epitaxial layer material having a second conductivity type dopant, the trenches extending from the first and second body regions to the substrate, the dopant being diffused from the trenches to the epitaxial crystals adjacent to the trenches In the part of the layer, the power MOSFET of item 1 of the patent application scope, wherein the material for filling the trench is polycrystalline silicon. 3. If the power M 0 S F E T of item 1 of the patent application scope, wherein the material filling the trench is a dielectric. 4 · If the power of the patent application No. 3 item M 0 S F ET is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the dielectric is silicon dioxide. 5. The power M 0 S F E T according to item 1 of the patent application scope, wherein the dopant is boron. 6. The power MOS F E T according to item 2 of the patent application scope, wherein the polycrystalline chopping system is at least partially oxidized. 7. The power MOS F E T as claimed in the scope of the patent application, wherein the polycrystalline silicon is subsequently recrystallized to form a single crystalline silicon. This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm) '~ -14- 499757 A8 B8 C8 D8 VI. Patent application scope 2 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8. The power MOSFET of item 1, wherein the material for filling the trench includes polycrystalline silicon and a dielectric. 9 · If the power M 0 S F E T of the scope of patent application is applied, wherein the body regions include deep body regions. 1 0. The power MOS F E T as claimed in item 6 of the patent application, wherein the polycrystalline silicon is subsequently recrystallized to form a single crystalline silicon. 11. A method for forming a power MOSFET, comprising the steps of: providing a substrate of a first conductivity type; depositing an epitaxial layer on the substrate, the epitaxial layer having the first conductivity type 9 forming a first and a second body region on In the Jiajing layer, a drift region is defined therebetween, and the body regions have a second conductivity type; first and second source regions of the first conductivity type are formed in the first and second body regions, respectively; The trenches are in the drift region of the epitaxial layer; the trenches are filled with a material dopant having a second conductivity type, and the trenches extend from the first and second body regions. To the base II; 'and at least a portion of the replacement WU dopant diffused from the trenches into the portion of the epitaxial layer adjacent to the trenches. 12. The method according to item 11 of the scope of the patent application, wherein the material of the ditch filling trench comprises polycrystalline silicon. 1 3 · If the material in the square g groove of item 11 of the scope of patent application is dielectric. Among them Wuchonggou -----__ ^-IΦ II Han (please read the precautions on the back before filling this page), 1T This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -15, Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 499757 A8 B8 C8 P8 ____ VI. Application scope of patent 3 1 4 · If the method of application scope No. 13 is applied, the dielectric is silicon dioxide. 1 5. The method according to item 11 of the scope of patent application, wherein the miscellaneous agent is boron. [16] The method according to item 12 of the scope of patent application 'further includes a step of at least partially oxidizing the polycrystalline silicon. 1 7 · The method according to item 12 of the scope of patent application 'additionally includes the step of recrystallizing the polycrystalline silicon to form a single crystal silicon ° 1 8 · The method according to item 11 of the scope of patent application' wherein the trench is filled with the Materials include polycrystalline silicon and dielectric. 19. The method according to item 11 of the scope of patent application, wherein the body regions include deep body regions. 20. The method according to item 11 of the scope of patent application, wherein the trench is formed by providing a mask layer defining at least one of the trenches and etching the trench defined by the mask layer. 2 1. The method according to item 11 of the patent application scope, wherein the body regions are formed by implanting and diffusing a dopant into the matrix. 2 2 · The method according to item 16 of the scope of patent application, further comprising the step of recrystallizing the polycrystalline silicon to form a single crystalline silicon. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) -16--16-
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