CN1941414B - A power mosfet and method of making same - Google Patents

A power mosfet and method of making same Download PDF

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Publication number
CN1941414B
CN1941414B CN2006101256294A CN200610125629A CN1941414B CN 1941414 B CN1941414 B CN 1941414B CN 2006101256294 A CN2006101256294 A CN 2006101256294A CN 200610125629 A CN200610125629 A CN 200610125629A CN 1941414 B CN1941414 B CN 1941414B
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groove
body region
field effect
oxide
conductivity type
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CN1941414A (en
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理查德·A·布兰查德
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General Semiconductor Inc
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General Semiconductor Inc
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Priority claimed from US09/586,407 external-priority patent/US6593619B1/en
Priority claimed from US09/849,036 external-priority patent/US6627949B2/en
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A power MOSFET is provided that includes a substrate of a first conductivity type (2). An epitaxial layer (1) also of the first conductivity type is deposited on the substrate. First and second body regions (5a, 6a, 5b, 6b) are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions (7, 8) of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches (44, 46) are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches to form the second conductivity type semiconductor region (40, 42) below the body regions.

Description

MOS field effect tube and manufacturing approach thereof
The application requires to submit on December 2nd, 2002, and application number is 01810605.6 (PCT/US01/17745), and denomination of invention is divided an application for the patent application of " MOS field effect tube and manufacturing approach thereof ".
Related application
This application is that U. S. application is entitled as the subsequent application of " the high-voltage power metal-oxide-semiconductor field effect transistor with low on-resistance value " for the 09/586th, No. 407, and the applying date of this application is on June 2nd, 2000.
Technical field
The present invention relates generally to semiconductor device, relate in particular to the MOS field effect tube device.
Background technology
The MOS field effect tube device is used for aspects such as motor vehicle electronic system, power supply and power management applications.These devices should be able to bear high voltage in the time of in off position, and when opening, can produce low-voltage and high saturation current density.
Shown in Figure 1 is the exemplary block diagram of the metal-oxide-semiconductor field effect transistor of N groove.In this device, the N silicon epitaxial layers 1 that on N+ silicon layer 2, forms comprises the N+ source area 7 and 8 of p body region (P-body regions) 5a and 6a and two metal-oxide-semiconductor field effect transistor sub-districts. P body region 5 and 6 can contain degree of depth p body region (deep P-body regions) 5b and 6b simultaneously.The surface portion of confirming of source electrode body electrode 12 extend past epitaxial loayers 1 contacts with source region and body region.In the accompanying drawing 1, N epitaxial loayer 1 part that extends to the semiconductor-on-insulator surface forms the N type drain electrode of two sub-districts.Provide drain electrode (not showing separately) in the bottom of N+ substrate 2.The gate electrode 18 of the insulation of oxide layer and polysilicon layer is positioned on the groove and drain electrode part of main body.
The conducting resistance major part of conventional metal-oxide-semiconductor field effect transistor shown in the accompanying drawing 1 is determined by the drift zone resistance in the epitaxial loayer 1.Conversely, drift zone resistance is determined by the doping level and the layer thickness of epitaxial loayer 1.Yet in order to improve the breakdown voltage value of this device, the doping content that must reduce epitaxial loayer 1 increases layer thickness simultaneously.Curve 20 is depicted as the on-resistance per unit value as conventional MOS FET puncture voltage value function in the accompanying drawing 2.Unfortunately, shown in curve 20, when the puncture voltage of device raise fast, the resistance of this device also raise fast.When metal-oxide-semiconductor field effect transistor is in higher voltage running status, when particularly being higher than a few hectovolt, the rapid growth of resistance will have problems.
Metal-oxide-semiconductor field effect transistor shown in the accompanying drawing 3 is more operated under the high-voltage state after being used to reduce conducting resistance.This metal-oxide-semiconductor field effect transistor is shown in 683 page of the 26.2nd chapter content of IEDM paper in 1998.This metal-oxide-semiconductor field effect transistor is similar with the FET of traditional M OS shown in the accompanying drawing 2, and different is that the former comprises the inner p type doped region 40 and 42 of drift region that is extended to device by body region 5 and 6 bottoms.The district (column) of the drift region that P type dopant area 40 and 42 has been confirmed to be opened by the separation of n type doped region, this n type doped region is such as by contiguous p doped region 40 and 42 the epitaxial loayer 1 affiliated determined district of part.The alternate area of contrary doping type not only can produce increasing of vertical direction reverse voltage in the conventional MOS FET, also is like this in the horizontal direction simultaneously.Consequently, the same as traditional device, the one-tenth-value thickness 1/10 of reduction epitaxial loayer 1 also improves after the drift region doping content, and this device can produce identical reverse voltage value equally.Curve 25 is depicted as as the conduction resistance value on the unit are of metal-oxide-semiconductor field effect transistor puncture voltage value function in the accompanying drawing 3 in the accompanying drawing 2.Clearly, under more high-tension situation, conducting resistance increases along with breakdown voltage value is linear basically in accompanying drawing 1 device, and the conduction resistance value of this device reduces greatly.
Operating characteristic in the accompanying drawing 3 after the device improvements is based on that electric charge in the transistor drift zone replenishes.That is to say that the doping in the drift region improves such as an one magnitude or higher greatly, offset additional charge through adding the counter-doping type area.Thereby transistorized blocking voltage value remains unchanged.When device was in opening, the electric charge additional area can not help the conduction of electric current.Transistorized these ideal characterisitics keys are to depend on the additional degree size of between the proximity of counter-doping type, accomplishing of electric charge.Unfortunately, the restrictive condition during the control procedure parameter in process of production is difficult to avoid distinguishing the lack of uniformity of doping gradient.For example, the diffusion along interface between interface between district and the substrate and district and the p body region can cause the variation of these near interface district part doping contents.
The sequence of operation that structure shown in the accompanying drawing 3 capable of using comprises a plurality of epitaxial deposition steps realizes that wherein all there is the interpolation of suitable alloy each epitaxial deposition steps back.Unfortunately, epitaxial deposition steps is carried out the expense limit for height, is uneconomic so make this structure.
Thereby, provide a kind of method of producing metal-oxide-semiconductor field effect transistor structure in the accompanying drawing 3 to be sought after.Deposition step is minimum can to reduce production costs thereby it requires, thereby can realize realizing electric charge high level between the counter-doping type adjacent region of enough control in the device drift region territory of procedure parameter additional simultaneously.
Summary of the invention
According to the present invention, the metal-oxide-semiconductor field effect transistor that is provided comprises the first conductivity type substrate.The epitaxial deposition that belongs to first conductivity type equally is at substrate.First and second body region are in epitaxial loayer and determined the drift region between the two.Body region has second conductivity type.First and second source areas of first conductivity type lay respectively in first and second body region.There are a plurality of grooves below the body region in the drift region of epitaxial loayer.The groove that these are extended to substrate by first and second body region is filled the material that comprises the second conductivity type alloy with the p-n laminated process.Alloy is diffused into the epitaxial loayer partial interior of adjacent trenches by groove, thereby forms the p type doped region that causes along the reverse voltage of level and vertical direction foundation.
Content according to an aspect of the present invention, the material of filling groove is a silicon.
Content according to a further aspect in the invention, the silicon of filling groove is partial oxidation at least.
Content according to other aspects of the invention, the material of filling groove is a dielectric, for example silicon dioxide etc.
Content according to other aspects of the invention, the material of filling groove can comprise silicon and dielectric.
Content can provide the method that forms metal-oxide-semiconductor field effect transistor according to other aspects of the invention.The method at first provides the first conductivity type substrate, then with epitaxial deposition on this substrate.Epitaxial loayer has first conductivity type.First and second body region form in epitaxial loayer to confirm the drift region between the two.Body region has second conductivity type.First and second source areas of first conductivity type are formed at respectively in first and second body region.In the drift region of epitaxial loayer, form a plurality of grooves.The material that comprises the second conductivity type alloy is inner at groove along epitaxial deposition.These grooves are extended to substrate by first and second body region.At least the part of alloy is diffused into the epitaxial loayer part of adjacent trenches by groove.
Description of drawings
Accompanying drawing 1 is depicted as the sectional view of conventional MOS field-effect tube structure.
Accompanying drawing 2 is depicted as a metal-oxide-semiconductor field effect transistor that makes up as the conduction resistance value on the unit are of conventional MOS FET puncture voltage function and according to the present invention.
Accompanying drawing 3 is depicted as to have to depress in same electrical and makes a farfetched comparison the metal-oxide-semiconductor field effect transistor structure that lower conducting resistance is operated on the said structural units of Fig. 1 area.
Accompanying drawing 4-6 is depicted as the relevant portion of the metal-oxide-semiconductor field effect transistor various embodiments constructed according to the present invention.
Accompanying drawing 7 is depicted as the complete metal-oxide-semiconductor field effect transistor constructed according to the present invention.
Embodiment
According to the present invention,, form the p type zone 40 and 42 shown in the accompanying drawing 3 at first around the also a pair of groove of p type zone 40 and 42 present position etchings.Next in these grooves, fill the material that is rich in alloy.Alloy in the material gets into the adjacent epitaxial layer that forms the device drift region territory by diffusing out in the groove.The formed alloy of epitaxial loayer partly forms p type zone.The related diffusion of the material of the filling groove also alloy of groove is kept in the resulting devices.Thereby, can not influence Devices Characteristics conversely thereby need material be selected.The material that can be used as filling groove that can enumerate comprises the polysilicon or the dielectric of silicon dioxide for example.
Accompanying drawing 4-6 is depicted as and can be used to be filled in the groove 44 of formation in the silicon epitaxial layers 1 and 46 several kinds of different blended condensation materials.Though accompanying drawing 4-6 provides groove 44-46, epitaxial loayer 1 and substrate 2, for clear, accompanying drawing 4-6 does not provide the upper part of the metal-oxide-semiconductor field effect transistor that comprises p body region and source area.
In the inventive embodiment, groove 44 and 46 inner fillings are by the doping dielectric, like the silicon dioxide of doped with boron shown in the accompanying drawing 4.After having filled groove, thereby boron diffusion forms p type zone 40 and 42 to adjacent epitaxial layer 1.The silicon dioxide of the doped with boron of filling groove is kept in the final metal-oxide-semiconductor field effect transistor.
In the inventive embodiment, groove is the polysilicon of partly filling doped with boron, i.e. polysilicon at least shown in the accompanying drawing 5.After having filled groove, thereby boron diffusion forms p type zone 40 and 42 to adjacent epitaxial layer 1.The polysilicon of the doped with boron of residue filling groove is kept in the final metal-oxide-semiconductor field effect transistor device.Alternately, diffusion finishes to form after the silicon dioxide, and polysilicon is oxidation whole or in part.Thereby the groove inside that is kept in the final metal-oxide-semiconductor field effect transistor device is filled with dielectric, i.e. silicon dioxide and any remaining polysilicon.In another substitutes, the polysilicon of any doped with boron in the groove can elevated temperature again crystallization to form monocrystalline silicon.In this case, monocrystalline silicon has been filled in the groove inside that remains in the final metal-oxide-semiconductor field effect transistor, or monocrystalline silicon and silicon dioxide or other dielectric mixture.
In the inventive embodiment, at first partly DOPOS doped polycrystalline silicon is filled in groove 44 and 46 shown in the accompanying drawing 6, then utilizes dielectric to deposit and fill up groove.After having filled groove, boron diffusion is arrived adjacent epitaxial layer 1 to form p type zone 40 and 42.The polysilicon of remaining doped with boron and be used for the dielectric of filling groove and be kept in the final metal-oxide-semiconductor field effect transistor device.Thereby the polysilicon elevated temperature of doped with boron carries out crystallization again and forms monocrystalline silicon in some cases.Thereby the groove inside that remains in the final metal-oxide-semiconductor field effect transistor is filled with monocrystalline silicon and dielectric.
Accompanying drawing 7 is depicted as the synthetic MOS field effect tube constructed according to the present invention.This metal-oxide-semiconductor field effect transistor comprises substrate 2, epitaxial loayer 1, p body region 5a and 6a, degree of depth p body region 5b and 6b, source area 7 and 8 and the p type zone 40 and 42 that is positioned respectively of groove 44 and 46.The district that opens by the separation of n type doped region has been confirmed in p type island region territory 40 and 42.Also provided among the figure and contained oxide layer 48 and the grid of polysilicon layer 49 and the source electrode that contains metal layer 50.
In another embodiment of the present invention, epitaxial deposition material can be filled in groove inside, like doped silicon.It possibly be favourable using epitaxial deposition in some cases, and reason is to reduce the formation of defective, thereby can strengthen the control of dopant gradient in the groove is obtained better uniformity simultaneously.As previously mentioned, be very important to the control of dopant gradient because more under the high operation voltage reduction key of the conduction resistance value of device to see the degree size that realizes that between the district of adjacent counter-doping thing type electric charge replenishes.Thereby, though need to use the step of additional epitaxial deposition in the embodiment of the invention, can obtain better electric charge and fill, this is very favourable.
Through the additional control of using the epitaxial deposition material filling groove to be provided, can be used for compensating the alloy inhomogeneities that near the district's partial interior the interface with substrate and p body region is occurred.It possibly be because when dopant goes out groove and forms the district that these inhomogeneities produce, due to the diffusion that between different layers, produces inevitably.For example in the accompanying drawing 7, when alloy is diffuseed to form p type zone 40 and 42 by groove 44 and 46, also can diffuse into p type regional 40 and 42 from the added dopant of dark doping p body region 5 and 6.Thereby, will mix more than the nubbin in flat pattern zone 40 and 42 near p type zone 40 and 42 parts of p body region 5 and 6.
Through extension deposit a material in the groove that doping content reduces gradually, can solve a difficult problem noted earlier." classification epi " technology of utilization can solve this difficult problem.That is to say that in epitaxial deposition process, doping content can increase or reduce gradually.For the method, the single alloy source electrode with specific atoms concentration can be used to produce the dopant levels of certain limit.Alternately, through settling two or more crystal silicon source electrodes that can be doped to variable concentrations can solve this difficult problem equally.In the rear half stage of epitaxial deposition process, having more, single source electrode or a plurality of source electrode of low doping concentration can be mainly used to reduce the doping content that obtains layer near the groove of p body region.Confirm when district when carrying out follow-up diffusing step, the added dopant material that comes from the p body region will be diffused in the p type district, thus original lower doping content in the compensation epitaxially deposited layer.Certainly, some current those of ordinary skill can be recognized the district of evenly mixing in order to obtain, various procedure parameters, as the quantity of different source electrodes, they doping content and never need optimised with time interval of source electrode deposition step etc.
Can use same technology to compensate the doping content of the reduction that the p type district part near substrate produced.In the case, in the initial rank district of epitaxial deposition process filling groove, having more, single source electrode or a plurality of source electrode of high-dopant concentration can be mainly used to improve the doping content near the epitaxial loayer that is arranged in groove of substrate.
The metal-oxide-semiconductor field effect transistor of invention can make up according to any conventional process technology shown in the accompanying drawing 7.For example, can adopt following series of steps of being lifted to accomplish accompanying drawing 7 described metal-oxide-semiconductor field effect transistors.
At first, the surperficial this method of utilizing oxide layer to cover epitaxial loayer 1 forms the oxidation mask layer, and oxide layer wherein can be made public as usually then, and composition is to remain the mask part of confirming groove 44 and 46 positions.Be implemented in dry state etching on the groove to penetrate the mask mouth through reactive ion etching, common depth bounds is the 10-40 micron.The limit wall of each groove can be level and smooth.At first, can use dry chemical etch to remove very thin oxide layer (common about 500-1000A) thereby the destruction that elimination is caused owing to the reactive ion etching process from ditch trough rim wall.Next, groove 44 and 46 and mask part on form the silicon dioxide layer (sacrificial silicon) of sacrificing.Silicon dioxide layer and the mask part that can remove sacrifice through buffer oxide etching or HF etching, thus resulting ditch trough rim wall is smooth as much as possible.
Groove 44 and 46 inside are filled with any material of before having mentioned, like polysilicon, silicon dioxide, silicon or their mixing.In deposition process, polysilicon or the oxide alloy that will mix especially is like boron.Next will accomplish diffusing step is dopant to be gone out groove enter into epitaxial loayer on every side.If the material that remains in the groove is a polysilicon, can be with its oxidation or crystallization again.
Next, utilize the exposure mask process to form the mask layer that certain figure is used for confirming source area 7 and 8.Then utilize injection and diffusion process to form source area 7 and 8.For example, when 80KeV, arsenic is injected into source area and reaches particular range 2 * 10 15To 1.2 * 10 16/ cm 2Between a concentration value.Expand to about 0.5 to 2.0 micron degree of depth through injecting back arsenic.The degree of depth of degree of depth p body region approximately is within 2.5 to 5 microns these specific scopes, and the body region degree of depth is approximately between the 1-3 micron.At last, remove mask layer to form accompanying drawing 7 said structures with traditional method.
Utilize classical pathway to form contact opening and accomplish the DMOS transistor through formation and setting oxide layer.Metal layer 50 also will deposit and form mask to confirm source electrode and grid.Use the filling mask also can confirm to fill the contact.At last, drain electrode contact layer (not providing) is formed on the substrate lower surface.
Be noted that in the formerly said process that before p body region and degree of depth p body region form, form groove, the present invention generally includes more process, groove can form before or after any one or whole residual doped region in these processes.And, though disclosed be a particular process that makes up metal-oxide-semiconductor field effect transistor, within scope of the present invention, can use other processing procedure.
Constructed metal-oxide-semiconductor field effect transistor has numerous advantages than the device of the prior art of utilizing conventional art to build according to the present invention.For example, the vertical dopant gradient in p type zone almost approaches 0.The alloy quantity that horizontal dopant gradient can be introduced through conversion and in diffusing step employed thermodynamic cycle number of times and cycle accurately control.Thereby alloy quantity and the side dopant gradient introduced can be able to change puncture voltage and the conduction resistance value of optimizing this device further.
In embodiments of the invention shown in the accompanying drawing 7, p type channel shaped is formed in the body region bottom.Yet, be not that each p type groove all needs with it relevant body region, particularly on the periphery of mould or comprise the zone of filler or tie point.
Though enumerate especially here and describe various embodiment, should be noted that for change of the present invention and change and all include among superincumbent description and the appended claim scope, and can not deviate from spirit of the present invention and category.For example, MOS field effect tube is provided according to the present invention, wherein the conductivity of various semiconductor regions can be with described related content be opposite here.

Claims (14)

1. MOS field effect tube comprises:
The first conductivity type substrate;
Epitaxial loayer on the substrate, said epitaxial loayer has first conductivity type;
Be positioned at first epitaxial loayer and confirmed first and second body region of drift region, said body region has second conductivity type;
Lay respectively at first and second source regions of first conductivity type in first and second body region;
Be positioned at a plurality of grooves below the body region of epitaxial loayer drift region; These groove groove inside are filled with the material that contains the second conductivity type alloy; Said groove extends to substrate from first and second body region, and said alloy is diffused into the epitaxial loayer part of adjacent trenches from said groove
The material of filling in the wherein said groove comprises a plurality of layers, and said a plurality of layers comprise that the interface layer that is adjacent to one of body region, said interface layer have the doping content lower than the internal layer of layered material.
2. metal-oxide-semiconductor field effect transistor as claimed in claim 1, the material of wherein said filling groove are silicon.
3. metal-oxide-semiconductor field effect transistor as claimed in claim 1, the material of wherein said filling groove are dielectric.
4. metal-oxide-semiconductor field effect transistor as claimed in claim 3, wherein said dielectric are silicon dioxide.
5. metal-oxide-semiconductor field effect transistor as claimed in claim 1, wherein said alloy are boron.
6. metal-oxide-semiconductor field effect transistor as claimed in claim 2 is that part is oxidized at least on the surface of the silicon layer of wherein said silicon in groove.
7. metal-oxide-semiconductor field effect transistor as claimed in claim 1, wherein the material of filling groove comprises silicon and dielectric.
8. metal-oxide-semiconductor field effect transistor as claimed in claim 1, wherein said body region comprises dark body region.
9. metal-oxide-semiconductor field effect transistor as claimed in claim 1, the epitaxial loayer part of wherein said adjacent trenches is at the concentration value uniformly that has in a lateral direction substantially of groove.
10. method that forms metal-oxide-semiconductor field effect transistor comprises step:
The first conductivity type substrate is provided;
Deposit epitaxial layers on substrate, said epitaxial loayer has first conductivity type;
In epitaxial loayer, form first and second body region between them, to confirm drift region, said body region has second conductivity type;
In first and second body region, form first and second source regions of first conductivity type respectively; And
In said epitaxial loayer drift region, form a plurality of grooves;
Deposition has the dielectric of the second conductivity type alloy in said groove; Said groove is extended to substrate by first and second body region; And this deposition step comprises a plurality of layers of deposition; Said a plurality of layer comprises that the interface layer that is adjacent to one of body region, said interface layer have the doping content lower than the internal layer of layered material;
The said alloy of at least a portion is diffused into the epitaxial loayer part that is adjacent to groove by said groove,
Wherein said body region comprises dark body region.
11. method as claimed in claim 10, wherein through providing mask layer to confirm that at least one groove forms said groove, etching is by the determined groove of mask layer simultaneously.
12. method as claimed in claim 10 wherein distributes with respect to doping content in the substrate proximity zone, said layered material has the doping content of reduction in the adjacent domain of body region.
13. method as claimed in claim 10, the epitaxial loayer part of wherein said adjacent trenches is at the concentration value uniformly that has in a lateral direction substantially of groove.
14. method as claimed in claim 12, the epitaxial loayer part of wherein said adjacent trenches is at the concentration value uniformly that has in a lateral direction substantially of groove.
CN2006101256294A 2000-06-02 2001-06-01 A power mosfet and method of making same Expired - Fee Related CN1941414B (en)

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US09/586,407 US6593619B1 (en) 1999-06-03 2000-06-02 High voltage power MOSFET having low on-resistance
US09/849,036 2001-05-04
US09/849,036 US6627949B2 (en) 2000-06-02 2001-05-04 High voltage power MOSFET having low on-resistance

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US5869875A (en) * 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact

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