Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
  • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

• the invention relates to a highly integrated semiconductor memory having a columnar EPROM cell with a floating gate and a control gate.
• the invention further relates to a method for producing such a semiconductor memory.
• a higher integration density can be achieved with a vertical design of the EPROM cells in the form of cylindrical or columnar transistors.
• stacked gate flash cells With a cell area of approximately
• the object of the invention is to create a semiconductor memory of the type mentioned at the outset, which can also be lithographic dimensions works reliably.
• a method for producing such a memory is to be created.
• the column-shaped or cylindrical EPROM cells are made so thin that they are completely depleted, the control gate directly at least in a partial area with an interposed insulator layer arranged in the column and the control gate formed from p + -doped semiconductor material.
• the completely depleted cylinders ensure very good threshold behavior. Due to the p + -doped control gate, the threshold voltage of the transistor on the drain side is sufficiently large, even with a small oxide thickness, which ensures safe blocking behavior.
• the threshold voltage is slightly more than 0.9 V.
• the floating gate transistor In the initial state, the floating gate transistor conducts, since the threshold voltage in the case of fully depleted NMOS with n + doped floating gate assumes negative values due to the work function
• the EPROM cells can be programmed to more positive values by shifting the threshold voltage, preferably with hot charge carriers with a positive voltage at the drain.
• the extremely thin cylinders achieve a very high integration density with a cell area of approximately 1.5 * F 2 if the etching masks for the cylinders are produced by an orthogonal spacer technique as described in the older German patent application 195 26 011.
• the EPROM cells are designed as split gate flash cells.
• the control gate is only separated from the completely depleted cylinder in a partial area by a thin insulator layer.
• the invention can also be implemented with stacked gate flash cells.
• the EPROM cells are preferably manufactured using silicon technology.
• the principle of the semiconductor memory according to the invention is also conceivable in germanium or gallium arsenide technology.
• etching masks are produced on a p-doped substrate wafer, anisotropic etching for producing the columns is carried out with the etching masks, an n + implantation is carried out in the source regions, the columns are cleaned and an oxide is grown on the columns and the surfaces in between, n + -doped polysilicon is deposited to form the floating gate and is removed in the area of the surfaces between the columns by anisotropic etching, on which n + -doped polysilicon, an interpolydielectric is deposited, a planarizing medium is deposited and etched back onto the lower column area, the interpoly dielectric and the first polysilicon layer above the planarizing medium are isotropically etched so that the planarizing medium is removed again
• a gate oxide is grown on the etched-off areas, a p + -doped polysilicon layer is deposited thereon to form the control gate
• the etching mask is produced by etching an auxiliary layer with two intersecting spacer lines, the areas of the spacer lines formed grid forms the etching mask.
• the distance of the parallel spacer lines from one another is determined by the size F that can be achieved by photolithography.
• the width of the individual spacer lines is only determined by the layer thickness of the spacer layer used and the spacer technique and not by the structural fineness of the photo technique. The crossing regions of the spacer lines formed in this way can therefore be produced by almost a factor 4 smaller than the structures produced directly by photolithography.
• An element of the fifth main group and in particular arsenic is preferably used for n + doping of the source regions.
• the side wall polymers which formed during the etching of the columns and also mask the implantation are expediently etched isotropically after the implantation. In this way, the side wall polymers formed as a by-product during the etching can simultaneously guarantee an unclean manufacturing process as an implantation mask.
• ONO is preferably produced or deposited as an interpolydielectric by oxidation on the first, n + " doped polysilicon layer which forms the floating gate.
• Lacquer is preferably used as the planarizing medium, since it is easy to apply and etch back, and selectively the other materials can be removed.
• the columns are produced in the word line direction with a smaller spacing from one another than in the bit line direction. It is particularly advantageous to etch back the second polysilicon layer that forms the control gate to such an extent that there is a connection between the control gates of the individual columns or cells in the word line direction and not in the bit line direction. This creates a self-aligned word line.
• the invention is explained in more detail below on the basis of an exemplary embodiment shown in the schematic drawing. Show in detail
• etching mask 1 shows a p + -doped substrate 1 which forms part of a wafer.
• Sublithographic etching masks are created on this flat substrate wafer by applying an oxide layer and an overlying auxiliary poly-silicon layer, by using intersecting spacer lines to produce an etching mask 2, the structure size of which is determined only by the layer thickness and the spacer technology.
• the etching masks 2 shown are produced with the thin residual layer of amorphous silicon or polysilicon 3 still above them.
• the oxide etching masks are either thermally oxidized or produced by a TEOS deposition. The use of nitride is also possible.
• FIG. 2 shows how the substrate 1 is etched anisotropically with this etching mask 2, so that the columns 4 are formed.
• the arrows denoted by 5 in FIG. 3 symbolize the common source implantation (common source implantation) into the etched back substrate areas.
• the substrate regions doped with arsenic n + " are provided with reference number 6.
• RIE etching reactive ion etching
• 4 polymers have formed on the side walls of the columns, which form a protective layer 7 on the columns and thus prevent implantation in the columns After the implantation, the polymers of the protective layer 7 are removed and the silicon isotropically overetched in order to obtain clean surfaces on the side walls of the columns 4.
• FIG. 4 shows that a tunnel oxide 8 has been applied to the cleaned columns 4, preferably by growth, and a layer n + doped polysilicon has been deposited. This polysilicon layer 9 is used to form the floating gate.
• the poly-silicon layer 9 is etched on the back-etched substrate regions in an anisotropic selective etching. In this case, the part of the polysilicon layer on the tips of the columns 4 is also removed, and roundings or bulges occur at the corners of the column tips.
• An interpolydielectric 10 is then produced by oxidation or deposition. ONO is preferably used for this purpose.
• a planarizing medium 11, in particular lacquer, is deposited thereon and etched back to such an extent that the lower region of the columns 4 is covered.
• the sandwich of interpolydielectric 10 and the n + " doped polysilicon layer 9 is isotropically etched back above the planarizing medium 11 and preferably by plasma etching down to the column 4. Then the planarizing medium 11 is completely removed and a gate oxide 12 of the series transistor The split gate cell has grown thermally, so that an n + -doped ring from the first polysilicon layer 9 is left in the lower region of the columns 4, which is the floating Gate 14 forms.
• a second polysilicon layer 13, which is doped with p + " is deposited on the gate oxide 12 or the remaining interpolydielectric layer 10. This second silicon layer 13 serves to form the control gate. This process state is shown in FIG. 6.
• FIG. 7 and 8 show how the second polysilicon layer 13 is anisotropically etched, so that a second spacer ring is formed which completely surrounds the first spacer ring.
• This second spacer ring forms the control gate 15 of the split gate flash EPROM cell, which completely surrounds the floating gate 14.
• the thickness of the second polysilicon layer 13 is selected such that it is etched back in one direction up to the etched-back substrate base during the anisotropic etching. This is shown in FIG. 7. 8 shows a section through the direction perpendicular thereto, in which the columns 4 are somewhat closer to one another, so that the control gates 15 each have an overlap with the control gate 15 of the neighboring cell.
• a self-aligned word gate self-aligned control gate
• the remaining tip of the column 4 is n + -doped.
• This n + " doped region is identified in FIG. 10 by reference numeral 16.
• the column tip serves to form the drain connection and is doped with the same conductivity type as the source connection in the likewise n +" doped substrate regions 6.
• a planarizing oxide 17 is applied and etched back up to the upper limit of the columns 4.
• a TEOS layer with a suitable thickness can also be deposited and etched back by CMP (Chemo Mechanical Polishing). Only then does the implant tion in the areas 16, since the underlying gate areas are protected by the planarizing oxide 17.
• the drain contacts are connected by a metal track 18. The metal path is continuous in the direction of the bit line.
• the metal tracks 18 are therefore only formed along the bit line direction.
• the metal tracks 18 are also produced by spacer technology, e.g. by CVD deposition of tungsten on an auxiliary oxide layer.
• FIG. 12 A plan view of a cross-sectional periodic memory cell array produced in this way is shown in FIG. 12. This shows the columns 4 with the floating gate 14 surrounding them and the control gate 15 formed around them. In the word line direction, the control gate 15 form an overlap, so that a self-aligned word line is formed. The control gates 15 are separated from one another in the bit line direction, but there is a connection by means of the metal tracks 18 indicated by dashed lines.
• a memory cell has a size of approximately 1.0 F in the direction of the word line and 1.5 F in the direction of the bit line. In terms of functionality, the individual memory cells correspond to the conventional split gate flash cells. The completely depleted cylinders suggest very good sub-threshold behavior. Due to the p + " doped control gate, the threshold voltage of the split gate transistor on the drain side is sufficiently large even with a small oxide thickness.

Landscapes

• Non-Volatile Memory (AREA)
• Semiconductor Memories (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=7782235

Family Applications (1)

Country Status (10)

Families Citing this family (29)

Family Cites Families (15)

• 1996
  • 1996-01-05 DE DE19600307A patent/DE19600307C1/de not_active Expired - Fee Related
  • 1996-12-11 JP JP52472197A patent/JP3246917B2/ja not_active Expired - Fee Related
  • 1996-12-11 RU RU98114501/28A patent/RU2153210C2/ru not_active IP Right Cessation
  • 1996-12-11 UA UA98073472A patent/UA46079C2/uk unknown
  • 1996-12-11 WO PCT/DE1996/002386 patent/WO1997025744A1/de active IP Right Grant
  • 1996-12-11 CN CNB961995459A patent/CN1286182C/zh not_active Expired - Fee Related
  • 1996-12-11 KR KR10-1998-0705121A patent/KR100417449B1/ko not_active IP Right Cessation
  • 1996-12-11 EP EP96946072A patent/EP0956592A1/de not_active Withdrawn
• 1997
  • 1997-01-01 IN IN5CA1997 patent/IN190928B/en unknown
• 1998
  • 1998-07-06 US US09/111,120 patent/US6157060A/en not_active Expired - Fee Related

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events