DE69841847D1 - In harz gegossene halbleiteranordnung - Google Patents

In harz gegossene halbleiteranordnung

Info

Publication number
DE69841847D1
DE69841847D1 DE69841847T DE69841847T DE69841847D1 DE 69841847 D1 DE69841847 D1 DE 69841847D1 DE 69841847 T DE69841847 T DE 69841847T DE 69841847 T DE69841847 T DE 69841847T DE 69841847 D1 DE69841847 D1 DE 69841847D1
Authority
DE
Germany
Prior art keywords
casted
resin
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841847T
Other languages
English (en)
Inventor
Masanori Minamio
Satoru Konishi
Yoshihiko Morishita
Yuichiro Yamada
Fumito Itoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26414858&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69841847(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Panasonic Corp filed Critical Panasonic Corp
Application granted granted Critical
Publication of DE69841847D1 publication Critical patent/DE69841847D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE69841847T 1997-06-27 1998-06-08 In harz gegossene halbleiteranordnung Expired - Lifetime DE69841847D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP17139597 1997-06-27
JP7371198A JP2915892B2 (ja) 1997-06-27 1998-03-23 樹脂封止型半導体装置およびその製造方法
PCT/JP1998/002544 WO1999000826A2 (en) 1997-06-27 1998-06-08 Resin molded type semiconductor device and a method of manufacturing the same

Publications (1)

Publication Number Publication Date
DE69841847D1 true DE69841847D1 (de) 2010-09-30

Family

ID=26414858

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841847T Expired - Lifetime DE69841847D1 (de) 1997-06-27 1998-06-08 In harz gegossene halbleiteranordnung

Country Status (8)

Country Link
US (1) US6900524B1 (de)
EP (1) EP0996962B1 (de)
JP (1) JP2915892B2 (de)
KR (1) KR100397539B1 (de)
CN (2) CN100423253C (de)
DE (1) DE69841847D1 (de)
TW (1) TW384534B (de)
WO (1) WO1999000826A2 (de)

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MY133357A (en) 1999-06-30 2007-11-30 Hitachi Ltd A semiconductor device and a method of manufacturing the same
JP3768762B2 (ja) * 2000-02-03 2006-04-19 ローム株式会社 樹脂パッケージ型半導体装置
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
US6483178B1 (en) * 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
JP4547086B2 (ja) 2000-12-25 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置
JP3895570B2 (ja) 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6882048B2 (en) * 2001-03-30 2005-04-19 Dainippon Printing Co., Ltd. Lead frame and semiconductor package having a groove formed in the respective terminals for limiting a plating area
JP2003204027A (ja) 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
JP2003224239A (ja) * 2002-01-29 2003-08-08 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US6841854B2 (en) 2002-04-01 2005-01-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device
KR100975692B1 (ko) * 2002-07-01 2010-08-12 가부시끼가이샤 르네사스 테크놀로지 반도체 장치
JP2004335710A (ja) * 2003-05-07 2004-11-25 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2005159103A (ja) 2003-11-27 2005-06-16 Renesas Technology Corp 半導体装置およびその製造方法
US20050167796A1 (en) * 2004-01-29 2005-08-04 Tay Kheng C. Miniaturised surface mount optoelectronic component
MY136216A (en) * 2004-02-13 2008-08-29 Semiconductor Components Ind Method of forming a leadframe for a semiconductor package
JP2006108306A (ja) * 2004-10-04 2006-04-20 Yamaha Corp リードフレームおよびそれを用いた半導体パッケージ
US20060131708A1 (en) * 2004-12-16 2006-06-22 Ng Kee Y Packaged electronic devices, and method for making same
US8138586B2 (en) * 2005-05-06 2012-03-20 Stats Chippac Ltd. Integrated circuit package system with multi-planar paddle
JP4055175B2 (ja) * 2005-10-07 2008-03-05 ヤマハ株式会社 半導体パッケージ
JP4489791B2 (ja) * 2007-05-14 2010-06-23 株式会社ルネサステクノロジ Ｑｆｎパッケージ
JP2009032906A (ja) * 2007-07-27 2009-02-12 Seiko Instruments Inc 半導体装置パッケージ
JP5097639B2 (ja) * 2008-08-01 2012-12-12 ルネサスエレクトロニクス株式会社 リードフレーム及び半導体装置
US8072770B2 (en) * 2008-10-14 2011-12-06 Texas Instruments Incorporated Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
CN101859827A (zh) * 2009-04-07 2010-10-13 裕星企业有限公司 发光二极管
JP2010118712A (ja) * 2010-03-04 2010-05-27 Renesas Technology Corp Ｑｆｎパッケージの製造方法
JP2015153987A (ja) * 2014-02-18 2015-08-24 株式会社デンソー モールドパッケージ
JP2015177080A (ja) * 2014-03-15 2015-10-05 新日本無線株式会社 リード内蔵型回路パッケージ及びその製造方法
JP6253531B2 (ja) * 2014-06-30 2017-12-27 ルネサスエレクトロニクス株式会社 半導体装置
CN104505379A (zh) * 2014-12-19 2015-04-08 日月光封装测试(上海)有限公司 导线框架条及使用该导线框架条的半导体封装体
WO2016203787A1 (ja) * 2015-06-18 2016-12-22 シャープ株式会社 送風装置
CN107924884B (zh) * 2016-03-30 2022-02-18 松下知识产权经营株式会社 半导体装置

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JPH0621304A (ja) 1992-07-06 1994-01-28 Seiko Epson Corp リードフレーム及び半導体装置の製造方法
JPH0685132A (ja) 1992-09-07 1994-03-25 Mitsubishi Electric Corp 半導体装置
JPH06104364A (ja) 1992-09-22 1994-04-15 Sony Corp リードフレーム、これを用いた半導体チップのモールド方法及びモールド用金型
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JP3136029B2 (ja) 1993-08-09 2001-02-19 株式会社日立製作所 半導体装置
JP3233507B2 (ja) * 1993-08-13 2001-11-26 株式会社東芝 半導体装置
DE69530037T2 (de) * 1994-09-22 2003-10-16 Nec Electronics Corp Automatische Bandmontage für Halbleiteranordnung
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Also Published As

Publication number Publication date
CN101114629B (zh) 2011-05-11
KR100397539B1 (ko) 2003-09-13
EP0996962A2 (de) 2000-05-03
TW384534B (en) 2000-03-11
KR20010013562A (ko) 2001-02-26
CN1268246A (zh) 2000-09-27
CN100423253C (zh) 2008-10-01
JP2915892B2 (ja) 1999-07-05
EP0996962B1 (de) 2010-08-18
WO1999000826A3 (en) 1999-05-27
US6900524B1 (en) 2005-05-31
JPH1174440A (ja) 1999-03-16
WO1999000826A2 (en) 1999-01-07
CN101114629A (zh) 2008-01-30

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