JP2005159103A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2005159103A JP2005159103A JP2003396996A JP2003396996A JP2005159103A JP 2005159103 A JP2005159103 A JP 2005159103A JP 2003396996 A JP2003396996 A JP 2003396996A JP 2003396996 A JP2003396996 A JP 2003396996A JP 2005159103 A JP2005159103 A JP 2005159103A
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- back surface
- sealing body
- chip mounting
- semiconductor device
- resin
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Abstract
【解決手段】 半導体チップ2を樹脂封止する封止体と、前記封止体の内部に配置されたタブ1bと、タブ1bを支持する吊りリード1eと、それぞれの被接続面が前記封止体の裏面の周縁部に露出した複数のリードと、半導体チップ2のパッドと前記リードとをそれぞれ接続する複数のワイヤとからなり、吊りリード1eにおける前記封止体の外周部に配置された端部は、前記封止体の裏面側において露出せずに前記封止体によって覆われており、したがって、樹脂成形による吊りリード1eのスタンドオフは形成されないため、吊りリード切断時に、前記封止体の裏面の角部を切断金型の受け部の吊りリード1eの切断しろより十分に広い面積の平坦部によって支持することができ、レジン欠けの発生を防止してQFN(半導体装置)の品質の向上を図ることができる。
【選択図】 図12
Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の構造の一例を示す裏面図、図3は図1に示す半導体装置の角部の構造を示す拡大部分斜視図、図4は図1に示す半導体装置の構造を封止体を透過して示す平面図、図5は図4に示すA−A線に沿って切断した断面の構造を示す断面図、図6は図4に示すB−B線に沿って切断した断面の構造を示す断面図、図7は図4に示すA−A線に沿って切断した断面の構造の変形例を示す断面図、図8は図7に示す構造を封止体を透過して示す拡大部分平面図、図9は図1に示す半導体装置の角部の裏面のピン配置の一例を示す拡大部分裏面図、図10は本発明の実施の形態の変形例の半導体装置の構造を示す裏面図、図11は図1に示す半導体装置の製造方法の一例を示す組み立てフロー図、図12は図11に示す半導体装置の製造方法のモールド工程における板厚ゲート使用時の樹脂注入方法の一例を示す部分断面図、図13は図11に示す半導体装置の製造方法のモールド工程における通常ゲート使用時の樹脂注入方法の一例を示す部分断面図、図14は図12に示す板厚ゲート使用時のゲートとリードの位置関係の一例を示す拡大部分平面図、図15は図13に示す通常ゲート使用時のゲートとリードの位置関係の一例を示す拡大部分平面図、図16は図15に示すフレームの角部の構造を示す部分拡大平面図、図17は図11に示す半導体装置の製造方法のリード切断から個片化までの各工程における加工状態の一例を示す部分拡大断面図および部分拡大側面図、図18は図1に示す半導体装置の角部の裏面のピン配置の一例を示す拡大部分裏面図、図19は図13に示す通常ゲート使用時における半導体装置の角部の構造を示す拡大部分斜視図である。
1a リード
1b タブ(チップ搭載部)
1c チップ支持面
1d 裏面
1e 吊りリード
1f 裏面
1g 被接続面(一部)
1h 切断面
1i 肉厚部
1j 突出部
1k 間隙
1m 切断しろ
1n テーパ(面取り)
2 半導体チップ
2a パッド(電極)
2b 主面
2c 裏面
3 封止体
3a 裏面
3b レジンバリ
4 ワイヤ(金属細線)
5 QFN(半導体装置)
6 ダイボンド材
7 レジン注入経路
8 フィルムシート(封止用シート)
9 樹脂成形金型
9a 上型
9b 下型
9c キャビティ
9d 金型面
9e ゲート部
9f ランナ
10 切断金型
10a 受け部
10b 押さえ部
10c 平坦部
10d 切断パンチ
11 レーザ
Claims (15)
- 主面と、裏面と、その主面上に形成された半導体素子および複数の電極を有する半導体チップと、
前記半導体チップを樹脂封止する封止体と、
前記封止体の内部に配置されており、前記半導体チップと接続するチップ搭載部と、
前記チップ搭載部を支持する吊りリードと、
それぞれの一部が前記封止体の裏面の周縁部に露出しており、前記周縁部に並んで配置された複数のリードと、
前記半導体チップの前記複数の電極とこれに対応する前記複数のリードとをそれぞれ接続する複数のワイヤとを有し、
前記吊りリードにおける前記封止体の外周部に配置された端部は、前記封止体の裏面側において前記封止体によって覆われていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記チップ搭載部のチップ搭載側と反対側の裏面に突出部が設けられ、前記突出部は前記封止体の裏面に露出していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記吊りリードのチップ搭載側と反対側の裏面に突出部が設けられ、前記突出部は前記封止体の裏面に露出していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記チップ搭載部のチップ搭載側と反対側の裏面の中央部に突出部が設けられており、前記吊りリードのチップ搭載側と反対側の裏面に突出部が設けられ、前記チップ搭載部および前記吊りリードそれぞれの前記突出部は前記封止体の裏面に露出していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記チップ搭載部のチップ搭載側と反対側の裏面に突出部が設けられており、前記吊りリードのチップ搭載側と反対側の裏面の前記半導体チップの角部に対応した箇所に突出部が設けられ、前記チップ搭載部および前記吊りリードそれぞれの前記突出部は前記封止体の裏面に露出していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記チップ搭載部のチップ搭載側と反対側の裏面に複数の突出部が設けられており、前記吊りリードのチップ搭載側と反対側の裏面に突出部が設けられ、前記チップ搭載部および前記吊りリードそれぞれの前記突出部は前記封止体の裏面に露出していることを特徴とする半導体装置。
- 請求項6記載の半導体装置において、前記チップ搭載部および前記吊りリードは、それぞれの突出部領域を除いてそれ以外の領域がハーフエッチング加工されて成ることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記吊りリードは、そのチップ搭載側と反対側の裏面が前記封止体によって覆われて前記封止体の裏面に露出していないことを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記チップ搭載部の面積は前記半導体チップの面積よりも小さいことを特徴とする半導体装置。
- (a)チップ搭載部と、その周囲に配置された複数のリードと、前記チップ搭載部を支持する吊りリードとを有するリードフレームを準備する工程と、
(b)前記チップ搭載部に半導体チップを搭載する工程と、
(c)前記半導体チップの電極とこれに対応する前記リードとをワイヤで接続する工程と、
(d)樹脂成形金型の金型面に配置された封止用シート上に前記リードフレームを配置した後、前記リードフレームの前記複数のリードが前記封止用シートに密着するように前記樹脂成形金型の型締めを行い、その後、前記チップ搭載部および前記吊りリードそれぞれの裏面側に封止用樹脂を周り込ませて前記吊りリードの裏面の封止体の周縁部に対応した箇所が前記封止体によって覆われるように前記半導体チップおよび前記ワイヤを樹脂封止して前記封止体を形成する工程と、
(e)前記リードフレームから前記リードおよび前記吊りリードを分離して個片化する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、前記(d)工程で前記樹脂成形金型のキャビティに前記封止用樹脂を注入する際に、前記吊りリードの端部の外側を前記樹脂成形金型のゲート部で押さえ付けた状態で前記吊りリードの両脇のリード厚み分の間隙から前記キャビティに前記封止用樹脂を注入して前記樹脂封止を行うことを特徴とする半導体装置の製造方法。
- (a)樹脂成形金型の金型面に配置された封止用シート上に、チップ搭載部と吊りリードと複数のリードとを有するリードフレームを配置する工程と、
(b)前記(a)工程後、前記リードフレームの前記複数のリードが前記封止用シートに密着するように前記樹脂成形金型の型締めを行う工程と、
(c)前記(b)工程後、前記チップ搭載部および前記吊りリードそれぞれの裏面側に封止用樹脂を周り込ませて前記吊りリードの裏面の封止体の周縁部に対応した箇所が前記封止体によって覆われるように半導体チップを樹脂封止して前記封止体を形成する工程と、
(d)前記封止体の裏面側から切断パンチを進入させて前記複数のリードを切断する工程と、
(e)前記(d)工程後、前記封止体の表裏を反転させ、その後、前記封止体の表面に前記表面側からマーキングを行う工程と、
(f)前記封止体の表面側から前記切断パンチを進入させて前記吊りリードを切断する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、前記(f)工程で前記吊りリードを切断する際に、前記吊りリードの端部に対応した前記封止体の裏面の周縁部の箇所を、切断金型の前記吊りリードの切断しろより広い面積の平坦部によって支持した状態で切断することを特徴とする半導体装置の製造方法。
- チップ搭載部と、前記チップ搭載部に連結された吊りリードと、前記チップ搭載部の周囲に配置された複数のリードとを有するリードフレームと、
複数の半導体素子及び複数の電極を有し、前記チップ搭載部上に配置された半導体チップと、
前記半導体チップの前記複数の電極と前記複数のリードとを電気的に接続する複数のワイヤと、
表面と、前記表面と反対側の裏面と、前記表面と前記裏面の間の側面とを有し、かつ、前記半導体チップ、前記チップ搭載部、前記複数のワイヤ及び前記複数のリードを封止する樹脂体とを有し、
前記複数のリードの各々の一端部が前記樹脂体の前記裏面から露出され、
前記複数のリード及び前記吊りリードは、前記樹脂体の前記側面において、前記リードフレームの切断により生じる切断面を有し、
前記吊りリードの切断面は、前記樹脂体の裏面に達していないことを特徴とする半導体装置。 - 請求項14記載の半導体装置において、前記樹脂体の厚さ方向にける前記吊りリードの切断面の長さは、前記樹脂体の厚さ方向にける前記複数のリードの切断面の長さより短いことを特徴とする半導体装置。
Priority Applications (20)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003396996A JP2005159103A (ja) | 2003-11-27 | 2003-11-27 | 半導体装置およびその製造方法 |
US10/983,706 US7282396B2 (en) | 2003-11-27 | 2004-11-09 | Method of manufacturing a semiconductor device including using a sealing resin to form a sealing body |
KR20040097986A KR101054540B1 (ko) | 2003-11-27 | 2004-11-26 | 반도체 장치 및 그 제조 방법 |
US11/853,798 US20080006916A1 (en) | 2003-11-27 | 2007-09-11 | Method of Manufacturing a Semiconductor Device |
US12/277,144 US7691677B2 (en) | 2003-11-27 | 2008-11-24 | Method of manufacturing a semiconductor device |
US12/624,342 US7833833B2 (en) | 2003-11-27 | 2009-11-23 | Method of manufacturing a semiconductor device |
US12/624,309 US8053875B2 (en) | 2003-11-27 | 2009-11-23 | Method of manufacturing a semiconductor device |
US13/101,199 US8513785B2 (en) | 2003-11-27 | 2011-05-05 | Method of manufacturing a semiconductor device |
KR1020110061982A KR101054602B1 (ko) | 2003-11-27 | 2011-06-24 | 반도체 장치의 제조 방법 |
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US13/562,639 US8592961B2 (en) | 2003-11-27 | 2012-07-31 | Method of manufacturing a semiconductor device |
KR1020120085661A KR101277391B1 (ko) | 2003-11-27 | 2012-08-06 | 반도체 장치 |
KR1020130001922A KR101398311B1 (ko) | 2003-11-27 | 2013-01-08 | 반도체 장치 |
US14/070,676 US9024419B2 (en) | 2003-11-27 | 2013-11-04 | Method of manufacturing semiconductor device |
US14/702,969 US9425165B2 (en) | 2003-11-27 | 2015-05-04 | Method of manufacturing semiconductor device |
US15/236,143 US9806035B2 (en) | 2003-11-27 | 2016-08-12 | Semiconductor device |
US15/729,374 US10249595B2 (en) | 2003-11-27 | 2017-10-10 | Method of manufacturing a semiconductor device |
US16/290,804 US10998288B2 (en) | 2003-11-27 | 2019-03-01 | Method of manufacturing a semiconductor device |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242366A (ja) * | 1997-02-24 | 1998-09-11 | Ricoh Co Ltd | 半導体装置 |
JP2000036556A (ja) * | 1998-07-17 | 2000-02-02 | Matsushita Electronics Industry Corp | 半導体装置の製造方法とその半導体装置 |
JP2000307049A (ja) * | 1999-04-23 | 2000-11-02 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 |
JP2002261187A (ja) * | 2000-12-28 | 2002-09-13 | Hitachi Ltd | 半導体装置 |
JP2003197846A (ja) * | 2001-12-27 | 2003-07-11 | Mitsui High Tec Inc | リードフレームおよびこれを用いた半導体装置 |
JP2003332511A (ja) * | 2002-05-09 | 2003-11-21 | Mitsui High Tec Inc | リードフレームおよび半導体装置 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2002A (en) * | 1841-03-12 | Tor and planter for plowing | ||
JPS61139052A (ja) | 1984-12-11 | 1986-06-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路部品 |
JPS61220361A (ja) | 1985-03-26 | 1986-09-30 | Matsushita Electric Ind Co Ltd | 電子部品の捺印及びフレ−ム切断機 |
US5274914A (en) * | 1986-11-25 | 1994-01-04 | Hitachi, Ltd. | Method of producing surface package type semiconductor package |
JPH06232195A (ja) | 1993-01-28 | 1994-08-19 | Rohm Co Ltd | 半導体装置の製造方法およびリードフレーム |
JPH07235630A (ja) | 1994-02-25 | 1995-09-05 | Matsushita Electron Corp | リードフレーム |
JP3155933B2 (ja) * | 1996-03-29 | 2001-04-16 | キヤノン株式会社 | 電子写真用光透過性被記録材及び加熱定着方法 |
JP3012816B2 (ja) | 1996-10-22 | 2000-02-28 | 松下電子工業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP2915892B2 (ja) | 1997-06-27 | 1999-07-05 | 松下電子工業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP2951308B1 (ja) | 1998-03-13 | 1999-09-20 | 松下電子工業株式会社 | リードフレームの製造方法 |
JP2000091488A (ja) | 1998-09-08 | 2000-03-31 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材 |
MY133357A (en) * | 1999-06-30 | 2007-11-30 | Hitachi Ltd | A semiconductor device and a method of manufacturing the same |
KR20010037247A (ko) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | 반도체패키지 |
JP2001127090A (ja) | 1999-10-25 | 2001-05-11 | Matsushita Electronics Industry Corp | 樹脂封止型半導体装置の製造方法 |
JP2001156239A (ja) * | 1999-11-25 | 2001-06-08 | Matsushita Electronics Industry Corp | 半導体装置及び半導体装置の製造方法 |
JP2002091488A (ja) | 2000-01-31 | 2002-03-27 | Matsushita Electric Ind Co Ltd | 車載ナビゲーション装置 |
JP3547704B2 (ja) | 2000-06-22 | 2004-07-28 | 株式会社三井ハイテック | リードフレーム及び半導体装置 |
JP2002026190A (ja) | 2000-07-03 | 2002-01-25 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP4387566B2 (ja) | 2000-07-05 | 2009-12-16 | パナソニック株式会社 | 樹脂封止型半導体装置 |
JP3660861B2 (ja) | 2000-08-18 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4523138B2 (ja) | 2000-10-06 | 2010-08-11 | ローム株式会社 | 半導体装置およびそれに用いるリードフレーム |
KR20020048572A (ko) * | 2000-12-18 | 2002-06-24 | 정헌태 | 반도체 마킹 장비의 스트립 플리퍼 장치 |
US6700186B2 (en) | 2000-12-21 | 2004-03-02 | Mitsui High-Tec, Inc. | Lead frame for a semiconductor device, a semiconductor device made from the lead frame, and a method of making a semiconductor device |
JP4547086B2 (ja) * | 2000-12-25 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6828661B2 (en) * | 2001-06-27 | 2004-12-07 | Matsushita Electric Industrial Co., Ltd. | Lead frame and a resin-sealed semiconductor device exhibiting improved resin balance, and a method for manufacturing the same |
JP2003031753A (ja) | 2001-07-19 | 2003-01-31 | Sony Corp | 半導体装置及びその製造方法 |
US6710432B1 (en) * | 2001-11-02 | 2004-03-23 | National Semiconductor Corporation | Integrated circuit package with low inductance ground path and improved thermal capability |
JP3773855B2 (ja) * | 2001-11-12 | 2006-05-10 | 三洋電機株式会社 | リードフレーム |
JP2003158234A (ja) | 2001-11-21 | 2003-05-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6894376B1 (en) * | 2003-06-09 | 2005-05-17 | National Semiconductor Corporation | Leadless microelectronic package and a method to maximize the die size in the package |
JP2005159103A (ja) | 2003-11-27 | 2005-06-16 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7351611B2 (en) * | 2004-02-20 | 2008-04-01 | Carsem (M) Sdn Bhd | Method of making the mould for encapsulating a leadframe package |
-
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- 2003-11-27 JP JP2003396996A patent/JP2005159103A/ja active Pending
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- 2004-11-09 US US10/983,706 patent/US7282396B2/en active Active
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-
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- 2017-10-10 US US15/729,374 patent/US10249595B2/en active Active
-
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- 2019-03-01 US US16/290,804 patent/US10998288B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242366A (ja) * | 1997-02-24 | 1998-09-11 | Ricoh Co Ltd | 半導体装置 |
JP2000036556A (ja) * | 1998-07-17 | 2000-02-02 | Matsushita Electronics Industry Corp | 半導体装置の製造方法とその半導体装置 |
JP2000307049A (ja) * | 1999-04-23 | 2000-11-02 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法 |
JP2002261187A (ja) * | 2000-12-28 | 2002-09-13 | Hitachi Ltd | 半導体装置 |
JP2003197846A (ja) * | 2001-12-27 | 2003-07-11 | Mitsui High Tec Inc | リードフレームおよびこれを用いた半導体装置 |
JP2003332511A (ja) * | 2002-05-09 | 2003-11-21 | Mitsui High Tec Inc | リードフレームおよび半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014022399A (ja) * | 2012-07-12 | 2014-02-03 | Mitsui High Tec Inc | リードフレームおよびリードフレームの製造方法 |
JP2018157222A (ja) * | 2013-04-16 | 2018-10-04 | ローム株式会社 | 半導体装置 |
US10312171B2 (en) | 2013-04-16 | 2019-06-04 | Rohm Co., Ltd. | Semiconductor device |
JP2013168669A (ja) * | 2013-04-18 | 2013-08-29 | Agere Systems Inc | 改良型パドルを有するクワッド・フラット・ノーリード(qfn)集積回路(ic)パッケージおよびこのパッケージを設計する方法 |
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