CN104766843B - 一种可用smt工艺贴装的高功率半导体封装结构 - Google Patents

一种可用smt工艺贴装的高功率半导体封装结构 Download PDF

Info

Publication number
CN104766843B
CN104766843B CN201510202726.8A CN201510202726A CN104766843B CN 104766843 B CN104766843 B CN 104766843B CN 201510202726 A CN201510202726 A CN 201510202726A CN 104766843 B CN104766843 B CN 104766843B
Authority
CN
China
Prior art keywords
plastic packaging
packaging layer
pad
lead frame
high power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510202726.8A
Other languages
English (en)
Other versions
CN104766843A (zh
Inventor
金暎柱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bright Die Semiconductor Co Ltd In Nanjing
Original Assignee
Bright Die Semiconductor Co Ltd In Nanjing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bright Die Semiconductor Co Ltd In Nanjing filed Critical Bright Die Semiconductor Co Ltd In Nanjing
Priority to CN201510202726.8A priority Critical patent/CN104766843B/zh
Publication of CN104766843A publication Critical patent/CN104766843A/zh
Application granted granted Critical
Publication of CN104766843B publication Critical patent/CN104766843B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明公开了一种可用SMT工艺贴装的高功率半导体封装结构,包括若待封芯片、引线框架和塑封层,待封芯片焊接在引线框架上;引线框架一侧形成单管脚,另一侧形成双管脚;单管脚与焊盘一体成型,且焊盘前部存在方形突出部,该突出部内设有一圆形通孔,待封芯片的背面与该焊盘电性连接;双管脚通过键合线与待封芯片电性连接;塑封层形成并包覆于引线框架及待封芯片上,且至少塑封层的正面为全塑封面;管脚的端部暴露在外面;塑封层上也相应设置有圆形通孔,且其直径小于引线框架上的圆形通孔。本结构可以使用贴片机自动安装;效率高,品质好,人工成本低;解决了PCB板和主散热片及开关元器件间的绝缘问题,散热效果更好。

Description

一种可用SMT工艺贴装的高功率半导体封装结构
技术领域
本发明涉及一种可用SMT工艺贴装的高功率半导体封装结构,属于半导体分立器件的封装领域。
背景技术
半导体分立器件封装是将二极管、FET、IGBT等半导体芯片采用绝缘的树脂或陶瓷材料进行密封,在确保电性能的同时,起到固定、保护芯片及提高导热性能等作用。
现有的半导体分立器件封装形式包括TO-220/TO-3P/TO-247/TO-264
/TO-252/D2-PAK等,各封装形式又可因管脚数量、塑封面积不同细分为不同类型。
由于高功率半导体器件所用芯片面积大、能耗高、发热多,一般多采用TO-3P/TO-247/TO-264等插入式封装。另外的D2-PAK、TO-252封装虽可用表面贴装工艺(SMT)进行自动贴装,但体积较小,能装配芯片的面积和数量都较少,同时由于只能粘靠在PCB板上,器件散热性能严重受限,因此该封装形式只适用于小功率产品。
而TO-3P/TO-247/TO-264等封装形式在安装时都需要手动插入后进行人工焊接,在电路中使用数量又较多,通常需要8个以上并联,效率低,人工成本偏高;此外,由于人工操作的一致性限制,随着产量增加,该类产品的良率问题越来越低、安装费用越来越高,且管脚和主散热片之间、PCB和主散热片之间的绝缘问题也越来越显著。
发明内容
为解决上述技术问题,本发明提出一种可用SMT工艺贴装的高功率半导体封装结构,该封装结构效率高、散热效果好且结构合理。
为达到上述目的,本发明的技术方案如下:一种可用SMT工艺贴装的高功率半导体封装结构,包括:
—待封芯片,该待封芯片有若干个;
—引线框架,所述若干待封芯片焊接在该引线框架上;且该引线框架包括三个管脚,该三个管脚形成于两侧,一侧形成单管脚,一侧形成双管脚;
所述单管脚与焊盘一体成型,且焊盘前部存在方形突出部,该突出部内设有一圆形通孔,所述若干待封芯片的背面与该焊盘电性连接;
所述双管脚与焊盘分离,且形成于靠近圆形通孔的一侧,所述双管脚分布在焊盘方形突出部的两侧,且所述双管脚分别通过键合线与所述待封芯片电性连接;
—塑封层,所述塑封层形成并包覆于所述引线框架及待封芯片上,且至少塑封层的正面为全塑封面;所述管脚的端部暴露在塑封层外面,且其外露的管脚大小与PCB的焊盘大小相适应;
所述塑封层上设置有与引线框架上圆形通孔位置相适应的圆形通孔,且所述塑封层上的圆形通孔的直径小于引线框架上的圆形通孔的直径。
优选的,所述单管脚与双管脚均经过Z形折弯;且与所述单管脚一体成型的焊盘,其背面形成为一金属面;
优选的,做为本封装结构的一种外形结构,所述塑封层的正面为全塑封面,且所述金属面暴露在塑封层的背面。
优选的,做为本封装结构的另外一种外结构,所述塑封层的正面和背面均为全塑封面,且金属面被包裹在塑封层内。
优选的,所述塑封层的正面距离外露的管脚近,其背面距离外露的管脚远,且折弯后的双管脚底部高出与单管脚一体成型的焊盘H高度,且H为0mm-7mm,当H为0时,所述双管脚底部和与单管脚一体成型的焊盘处在同一水平面上。
优选的,所述塑封层的塑封材料为环氧塑封材料;所述引线框架由铜合金材质制成,具体的材质为铜-铁系或铜-镍-硅系或铜-铬系,当然也不限于上述的几种合金;塑封后所述管脚经电镀镍锡或者电镀镍以增加其可焊性;所述键合线采用铝质或铜质或银质或金质引线。
本发明的有益效果:与现有高功率半导体分立器件封装形式相比,本发明有下列优点:
A.本结构可以使用贴片机自动安装;相比手动插脚和人工焊接,效率高,品质好,人工成本低;
B.可以解决了PCB板和主散热片及开关元器件间的绝缘问题;
C.较TO-263/TO-252封装,本发明封装形式可装配芯片功率更高,数量更多,且因能安装螺丝,其金属面(Heat Sink)与主散热片之间的接触更紧密,更有利于主散热片的散热;
D.当组装数量较多时,选择适当的封装,可以减少并联组件的使用量;
E.本发明的封装结构减少了外部的各种铁屑及尘土进入焊机内部,即使是更大容量的风扇也不会出现各种污染及破坏的现象;
F.本发明的封装结构有效的将PCB板与主散热片进行了分离,减少了因散热片热量过大对PCB板造成的伤害,温度过大会导致PCB板变形;
G.安装PCB后,保护涂层的涂覆作业更方便,湿气渗入问题更易解决。
附图说明
图1为现有技术的封装器件安装示意图;
图2为本发明分立器件的安装示意图;
图3为本发明内部结构示意图的主视图;
图4为图3的封装外形图;
图5为图3的俯视图;
图6为图5的封装外形图;
图7为图3的仰视图;
图8为图7的一种封装外形图;
图9为图7的另一种封装外形图;
图10为本发明引线框架的主视图;
图11为图9的俯视图;
其中:1.待封芯片,2.引线框架,3.单管脚,4.双管脚,5.圆形通孔,6.键合线,7.塑封层,8.PCB,9.金属面,10.主散热片,11.螺丝,12突出部,13、分立器件,14、焊锡。
具体实施方式
下面结合实施例和具体实施方式对本发明作进一步详细的说明。
如图3和图11所示,一种可用SMT工艺贴装的高功率半导体封装结构,包括:
—待封芯片1,该待封芯片1有若干个;
—引线框架2,所述若干待封芯片1焊接在该引线框架2上;且该引线框架2包括三个管脚,该三个管脚形成于两侧,一侧形成单管脚3,一侧形成双管脚4;
所述单管脚3与焊盘一体成型,且焊盘前部存在方形突出部12,该突出部12内设有一圆形通孔5,所述若干待封芯片1的背面与该焊盘电性连接;
所述双管脚4与焊盘分离,且形成于靠近圆形通孔5的一侧,所述双管脚4分布在焊盘方形突出部12的两侧,且所述双管脚4分别通过键合线6与所述待封芯片1电性连接;
—塑封层7,所述塑封层7形成并包覆于所述引线框架2及待封芯片1上,且至少塑封层7的正面为全塑封面;所述管脚的端部暴露在塑封层7外面,且其外露的管脚大小与PCB8的焊盘大小相适应;
所述塑封层7上设置有与引线框架2上圆形通孔5位置相适应的圆形通孔,且所述塑封层7上的圆形通孔5的直径小于引线框架2上的圆形通孔5的直径。
优选的,所述单管脚3与双管脚4均经过Z形折弯,与所述单管脚3一体成型的焊盘,其背面形成为一金属面9;
如图8所示,其为本封装结构的一种外形结构,塑封层7的正面为全塑封面,且所述金属面9暴露在塑封层7的背面。
如图9所示,其为本封装结构的另外一种外形结构,塑封层7的正面和背面均为全塑封面,且金属面9被包裹在塑封层7内。
所述塑封层7的正面距离外露的管脚近,其背面距离外露的管脚远,且折弯后的双管脚4底部高出与单管脚3一体成型的焊盘H高度,且H为0mm-7mm,当H为0时,所述双管脚底部和与单管脚一体成型的焊盘处在同一水平面上。
所述塑封层7的塑封材料为环氧塑封材料;所述引线框架2由铜合金材质制成,具体的材质为铜-铁系或铜-镍-硅系或铜-铬系,然后也不限于上述的几种合金;塑封后所述管脚经电镀镍锡或者电镀镍以增加其可焊性;所述键合线6采用铝质或铜质或银质或金质引线。
将上述元器件封装好后形成分立器件13,如图2所示,本发明封装好的分立器件的安装过程为:将封装好的分立器件13,贴装在PCB 8上,并用焊锡14将分立器件13的管脚焊接在PCB8上;且分立器件13反面朝下形成于PCB8的镂空位置,且该分立器件13管脚以下的塑封体部分没入PCB8中并伸出PCB8;所述分立器件13背面的金属面9与主散热片10紧密连接,且通过螺丝11穿过圆形通孔5将金属面9与主散热片10紧密固定。金属面9与主散热片10紧密连接,可以进行有效的散热,且该分立器件13将主散热片10与PCB8进行了隔开,防止了主散热片10上的热量过大对PCB8带来的一系列伤害,比如过热变形。

Claims (10)

1.一种可用SMT工艺贴装的高功率半导体封装结构,其特征在于,包括:
—待封芯片(1),该待封芯片(1)有若干个;
—引线框架(2),所述若干待封芯片(1)焊接在该引线框架(2)上;且该引线框架(2)包括三个管脚,该三个管脚形成于两侧,一侧形成单管脚(3),一侧形成双管脚(4);
所述单管脚(3)与焊盘一体成型,且焊盘前部存在方形突出部(12),该突出部内设有一圆形通孔(5),所述若干待封芯片(1)的背面与该焊盘电性连接;
所述双管脚(4)与焊盘分离,且形成于靠近圆形通孔(5)的一侧,所述双管脚(4)分布在焊盘方形突出部(12)的两侧,且所述双管脚(4)分别通过键合线(6)与所述待封芯片(1)电性连接;
—塑封层(7),所述塑封层(7)形成并包覆于所述引线框架(2)及待封芯片(1)上,且至少塑封层(7)的正面为全塑封面;所述管脚的端部暴露在塑封层(7)外面,且其外露的管脚大小与PCB(8)的焊盘大小相适应;
所述塑封层(7)上设置有与引线框架(2)上圆形通孔(5)位置相适应的圆形通孔(5),且所述塑封层(7)上的圆形通孔(5)的直径小于引线框架(2)上的圆形通孔(5)的直径。
2.根据权利要求1所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述单管脚(3)与双管脚(4)均经过Z形折弯;且与所述单管脚(3)一体成型的焊盘,其背面形成为一金属面(9)。
3.根据权利要求2所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述塑封层(7)的正面为全塑封面,且所述金属面(9)暴露在塑封层(7)的背面。
4.根据权利要求2所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述塑封层(7)的正面和背面均为全塑封面,且所述金属面(9)被包裹在塑封层(7)内。
5.根据权利要求2-4任一项所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述塑封层(7)的正面距离外露的管脚近,其背面距离外露的管脚远,且折弯后的双管脚(4)底部高出与单管脚(3)一体成型的焊盘H高度,且H为0mm-7mm。
6.根据权利要求1所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述塑封层(7)的塑封材料为环氧塑封材料。
7.根据权利要求1所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述引线框架(2)由铜合金材质制成。
8.根据权利要求7所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述铜合金材质为铜-铁系或铜-镍-硅系或铜-铬系。
9.根据权利要求1所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,塑封后所述管脚经电镀镍锡或者电镀镍以增加其可焊性。
10.根据权利要求1所述的可用SMT工艺贴装的高功率半导体封装结构,其特征在于,所述键合线(6)采用铝质或铜质或银质或金质引线。
CN201510202726.8A 2015-04-24 2015-04-24 一种可用smt工艺贴装的高功率半导体封装结构 Active CN104766843B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510202726.8A CN104766843B (zh) 2015-04-24 2015-04-24 一种可用smt工艺贴装的高功率半导体封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510202726.8A CN104766843B (zh) 2015-04-24 2015-04-24 一种可用smt工艺贴装的高功率半导体封装结构

Publications (2)

Publication Number Publication Date
CN104766843A CN104766843A (zh) 2015-07-08
CN104766843B true CN104766843B (zh) 2017-10-10

Family

ID=53648588

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510202726.8A Active CN104766843B (zh) 2015-04-24 2015-04-24 一种可用smt工艺贴装的高功率半导体封装结构

Country Status (1)

Country Link
CN (1) CN104766843B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107546190A (zh) * 2016-06-28 2018-01-05 厦门芯晶亮电子科技有限公司 晶体管封装结构
CN107633288A (zh) * 2016-07-18 2018-01-26 上海复旦微电子集团股份有限公司 一种抗金属标签及其制造方法
CN109326572A (zh) * 2018-11-12 2019-02-12 鑫金微半导体(深圳)有限公司 一种新型to-220型半导体封装结构
CN112117251B (zh) * 2020-09-07 2022-11-25 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法
CN215266282U (zh) * 2021-04-14 2021-12-21 苏州汇川技术有限公司 一种功率半导体器件的封装结构
CN114364121A (zh) * 2022-02-08 2022-04-15 合肥惟新半导体科技有限公司 一种pcb模块及其控制系统

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
KR100546372B1 (ko) * 2003-08-28 2006-01-26 삼성전자주식회사 웨이퍼 레벨 칩 사이즈 패키지의 제조방법
JP2005159103A (ja) * 2003-11-27 2005-06-16 Renesas Technology Corp 半導体装置およびその製造方法
US20060035092A1 (en) * 2004-08-10 2006-02-16 Shin-Etsu Chemical Co., Ltd. Resin composition for sealing LED elements and cured product generated by curing the composition
JP5868043B2 (ja) * 2011-07-04 2016-02-24 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
CN104766843A (zh) 2015-07-08

Similar Documents

Publication Publication Date Title
CN104766843B (zh) 一种可用smt工艺贴装的高功率半导体封装结构
CN101752329B (zh) 带有堆积式互联承载板顶端散热的半导体封装及其方法
KR101013001B1 (ko) 효과적인 열 방출을 위한 선이 없는 반도체 패키지
CN103426839B (zh) 半导体封装
JP2009503865A (ja) 熱放散が高められたパッケージ化集積回路
US7551455B2 (en) Package structure
US9679833B2 (en) Semiconductor package with small gate clip and assembly method
US20060226521A1 (en) Semiconductor Package Having Integrated Metal Parts for Thermal Enhancement
CN102983114B (zh) 具有超薄封装的高性能功率晶体管
CN101073151A (zh) 具有增强散热性的半导体封装结构
CN102201449A (zh) 一种功率mos器件低热阻封装结构
JP2017108130A5 (zh)
CN105489571A (zh) 一种带散热片的半导体封装及其封装方法
CN104733413A (zh) 一种mosfet封装结构
CN106898591A (zh) 一种散热的多芯片框架封装结构及其制备方法
JP2009071269A (ja) 発光ダイオード装置
CN204761831U (zh) 一种pcb板封装散热结构
TW510158B (en) Heat dissipation structure for semiconductor device
CN104051397A (zh) 包括非整数引线间距的封装器件及其制造方法
CN201946588U (zh) 一种功率半导体器件的封装结构
CN106098919A (zh) 一种高导热高绝缘的led光引擎封装结构及制备方法
CN219435850U (zh) Mosfet芯片封装结构
CN101819955B (zh) 具有增强散热性的半导体封装结构
JPH04316357A (ja) 樹脂封止型半導体装置
CN202142517U (zh) 半导体散热封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant