DE60313705D1 - Methode zur Erzeugung einer Struktur mittels eines lithographisch hergestellten Musters - Google Patents

Methode zur Erzeugung einer Struktur mittels eines lithographisch hergestellten Musters

Info

Publication number
DE60313705D1
DE60313705D1 DE60313705T DE60313705T DE60313705D1 DE 60313705 D1 DE60313705 D1 DE 60313705D1 DE 60313705 T DE60313705 T DE 60313705T DE 60313705 T DE60313705 T DE 60313705T DE 60313705 D1 DE60313705 D1 DE 60313705D1
Authority
DE
Germany
Prior art keywords
producing
produced pattern
lithographically produced
lithographically
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60313705T
Other languages
English (en)
Other versions
DE60313705T2 (de
Inventor
Mitsuru Hasegawa
Akihiro Miyauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE60313705D1 publication Critical patent/DE60313705D1/de
Application granted granted Critical
Publication of DE60313705T2 publication Critical patent/DE60313705T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C33/00—Moulds or cores; Details thereof or accessories therefor
    • B29C33/42—Moulds or cores; Details thereof or accessories therefor characterised by the shape of the moulding surface, e.g. ribs or grooves
    • B29C33/424—Moulding surfaces provided with means for marking or patterning
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C43/00—Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor
    • B29C43/32—Component parts, details or accessories; Auxiliary operations
    • B29C43/36—Moulds for making articles of definite length, i.e. discrete articles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0075—Manufacture of substrate-free structures
    • B81C99/009—Manufacturing the stamps or the moulds
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/03—Processes for manufacturing substrate-free structures
    • B81C2201/036—Hot embossing
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0017—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor for the production of embossing, cutting or similar devices; for the production of casting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
DE60313705T 2002-08-01 2003-07-23 Methode zur Erzeugung einer Struktur mittels eines lithographisch hergestellten Musters Expired - Lifetime DE60313705T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002224327 2002-08-01
JP2002224327A JP3821069B2 (ja) 2002-08-01 2002-08-01 転写パターンによる構造体の形成方法

Publications (2)

Publication Number Publication Date
DE60313705D1 true DE60313705D1 (de) 2007-06-21
DE60313705T2 DE60313705T2 (de) 2008-01-17

Family

ID=30112978

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60313705T Expired - Lifetime DE60313705T2 (de) 2002-08-01 2003-07-23 Methode zur Erzeugung einer Struktur mittels eines lithographisch hergestellten Musters

Country Status (6)

Country Link
US (2) US7192529B2 (de)
EP (1) EP1387216B1 (de)
JP (1) JP3821069B2 (de)
KR (1) KR100543240B1 (de)
DE (1) DE60313705T2 (de)
TW (1) TWI227371B (de)

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US7396475B2 (en) * 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7256435B1 (en) * 2003-06-02 2007-08-14 Hewlett-Packard Development Company, L.P. Multilevel imprint lithography
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US8148251B2 (en) * 2004-01-30 2012-04-03 Hewlett-Packard Development Company, L.P. Forming a semiconductor device
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US7686970B2 (en) 2004-12-30 2010-03-30 Asml Netherlands B.V. Imprint lithography
US7691275B2 (en) * 2005-02-28 2010-04-06 Board Of Regents, The University Of Texas System Use of step and flash imprint lithography for direct imprinting of dielectric materials for dual damascene processing
JP3918003B2 (ja) 2005-03-10 2007-05-23 Ｔｄｋ株式会社 磁気記録媒体、記録再生装置およびスタンパー
JP4641835B2 (ja) * 2005-03-16 2011-03-02 リコー光学株式会社 位相シフター光学素子の製造方法及び得られる素子
WO2006130721A2 (en) * 2005-06-02 2006-12-07 The Board Of Trustees Of The University Of Illinois Printable semiconductor structures and related methods of making and assembling
JP2009523312A (ja) * 2005-09-07 2009-06-18 トッパン、フォウタマスクス、インク デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法
FR2893018B1 (fr) * 2005-11-09 2008-03-14 Commissariat Energie Atomique Procede de formation de supports presentant des motifs, tels que des masques de lithographie.
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KR100834511B1 (ko) * 2006-09-06 2008-06-02 삼성전기주식회사 임프린팅용 스탬퍼 제조방법
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JP5608462B2 (ja) * 2010-07-30 2014-10-15 株式会社フジクラ インプリントモールドの製造方法
JP2011002859A (ja) * 2010-10-04 2011-01-06 Hoya Corp 位相シフトマスクの製造方法及びテンプレートの製造方法
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JP5681552B2 (ja) * 2011-04-15 2015-03-11 株式会社フジクラ インプリントモールドの製造方法及びインプリントモールド
JP5656735B2 (ja) * 2011-05-13 2015-01-21 株式会社フジクラ インプリントモールドとその製造方法
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JP6089451B2 (ja) * 2012-05-30 2017-03-08 大日本印刷株式会社 ナノインプリントモールドおよびその製造方法
JP5937929B2 (ja) * 2012-09-04 2016-06-22 株式会社フジクラ インプリントモールドの製造方法
US9277642B2 (en) * 2013-03-05 2016-03-01 Eastman Kodak Company Imprinted bi-layer micro-structure method
CN104078329B (zh) * 2013-03-28 2019-05-28 中芯国际集成电路制造(上海)有限公司 自对准多重图形的形成方法
JP6384040B2 (ja) * 2013-11-11 2018-09-05 大日本印刷株式会社 パターン形成方法とこれを用いたインプリントモールドの製造方法およびそれらに用いるインプリントモールド
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Also Published As

Publication number Publication date
KR20040012563A (ko) 2004-02-11
TWI227371B (en) 2005-02-01
EP1387216A2 (de) 2004-02-04
KR100543240B1 (ko) 2006-01-20
JP3821069B2 (ja) 2006-09-13
EP1387216B1 (de) 2007-05-09
US20060138080A1 (en) 2006-06-29
JP2004071587A (ja) 2004-03-04
TW200402596A (en) 2004-02-16
EP1387216A3 (de) 2005-06-22
US20040023162A1 (en) 2004-02-05
US7192529B2 (en) 2007-03-20
DE60313705T2 (de) 2008-01-17
US7455789B2 (en) 2008-11-25

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