ATE451717T1 - Herstellungsverfahren - Google Patents

Herstellungsverfahren

Info

Publication number
ATE451717T1
ATE451717T1 AT04744316T AT04744316T ATE451717T1 AT E451717 T1 ATE451717 T1 AT E451717T1 AT 04744316 T AT04744316 T AT 04744316T AT 04744316 T AT04744316 T AT 04744316T AT E451717 T1 ATE451717 T1 AT E451717T1
Authority
AT
Austria
Prior art keywords
liquid layer
stamp
multilevel
produce
pattern
Prior art date
Application number
AT04744316T
Other languages
English (en)
Inventor
Alexander Bietsch
Bruno Michel
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE451717T1 publication Critical patent/ATE451717T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures
    • H01L2221/1021Pre-forming the dual damascene structure in a resist layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/946Step and repeat
AT04744316T 2003-09-29 2004-08-23 Herstellungsverfahren ATE451717T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03021935 2003-09-29
PCT/IB2004/002724 WO2005031855A1 (en) 2003-09-29 2004-08-23 Fabrication method

Publications (1)

Publication Number Publication Date
ATE451717T1 true ATE451717T1 (de) 2009-12-15

Family

ID=34384568

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04744316T ATE451717T1 (de) 2003-09-29 2004-08-23 Herstellungsverfahren

Country Status (9)

Country Link
US (1) US7446057B2 (de)
EP (1) EP1702359B1 (de)
JP (1) JP4726789B2 (de)
KR (1) KR100791443B1 (de)
CN (1) CN100483672C (de)
AT (1) ATE451717T1 (de)
DE (1) DE602004024585D1 (de)
TW (1) TWI313490B (de)
WO (1) WO2005031855A1 (de)

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US7323417B2 (en) 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7632087B2 (en) * 2003-12-19 2009-12-15 Wd Media, Inc. Composite stamper for imprint lithography
US9039401B2 (en) 2006-02-27 2015-05-26 Microcontinuum, Inc. Formation of pattern replicating tools
US7875547B2 (en) * 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
JP4290177B2 (ja) * 2005-06-08 2009-07-01 キヤノン株式会社 モールド、アライメント方法、パターン形成装置、パターン転写装置、及びチップの製造方法
WO2007030527A2 (en) * 2005-09-07 2007-03-15 Toppan Photomasks, Inc. Photomask for the fabrication of a dual damascene structure and method for forming the same
US7259102B2 (en) 2005-09-30 2007-08-21 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
GB0523163D0 (en) * 2005-11-14 2005-12-21 Suisse Electronique Microtech Patterning of conductive layers with underlying compressible spacer layer or spacer layer stack
JP4684984B2 (ja) * 2005-12-07 2011-05-18 キヤノン株式会社 半導体装置の製造方法と物品の製造方法
US7422981B2 (en) 2005-12-07 2008-09-09 Canon Kabushiki Kaisha Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
US7468330B2 (en) 2006-04-05 2008-12-23 International Business Machines Corporation Imprint process using polyhedral oligomeric silsesquioxane based imprint materials
DE102006030267B4 (de) 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US8093150B2 (en) 2006-09-19 2012-01-10 Infineon Technologies Ag Methods of manufacturing semiconductor devices and structures thereof
EP2104573B1 (de) 2007-01-16 2017-12-27 Koninklijke Philips N.V. Verfahren und system zur kontaktierung einer flexiblen folie mit einem substrat
US9889239B2 (en) 2007-03-23 2018-02-13 Allegiance Corporation Fluid collection and disposal system and related methods
US20090005747A1 (en) 2007-03-23 2009-01-01 Michaels Thomas L Fluid collection and disposal system having interchangeable collection and other features and methods relating thereto
JP2009069203A (ja) * 2007-09-10 2009-04-02 Fuji Xerox Co Ltd 高分子光導波路及びその製造方法
US20170004978A1 (en) * 2007-12-31 2017-01-05 Intel Corporation Methods of forming high density metal wiring for fine line and space packaging applications and structures formed thereby
JP4977121B2 (ja) * 2008-03-25 2012-07-18 富士フイルム株式会社 インプリント用モールド構造体及びそれを用いたインプリント方法、並びに磁気記録媒体の製造方法
WO2009158631A1 (en) 2008-06-26 2009-12-30 President And Fellows Of Harvard College Versatile high aspect ratio actuatable nanostructured materials through replication
EP2172168A1 (de) * 2008-10-01 2010-04-07 3M Innovative Properties Company Dentale Vorrichtung, Verfahren zur Herstellung einer dentalen Vorrichtung und Verwendung davon
US8021974B2 (en) * 2009-01-09 2011-09-20 Internatioanl Business Machines Corporation Structure and method for back end of the line integration
WO2011008961A1 (en) 2009-07-15 2011-01-20 Allegiance Corporation Fluid collection and disposal system and related methods
WO2011041193A1 (en) 2009-09-30 2011-04-07 3M Innovative Properties Company Systems and methods for making layered dental appliances from the outside in
US8721938B2 (en) 2009-09-30 2014-05-13 3M Innovative Properties Company Methods for making layered dental appliances
US8834752B2 (en) 2009-09-30 2014-09-16 3M Innovative Properties Company Systems and methods for making layered dental appliances
US8813364B2 (en) 2009-12-18 2014-08-26 3M Innovative Properties Company Methods for making layered dental appliances
CN102214601B (zh) * 2010-04-02 2014-07-30 中芯国际集成电路制造(上海)有限公司 双镶嵌结构形成方法
FR2974194B1 (fr) 2011-04-12 2013-11-15 Commissariat Energie Atomique Procede de lithographie
CN102760686B (zh) * 2011-04-27 2014-12-03 中芯国际集成电路制造(上海)有限公司 半导体器件、形成互连结构的方法
CN102800623A (zh) * 2011-05-26 2012-11-28 中芯国际集成电路制造(上海)有限公司 形成双镶嵌结构的方法
US9589797B2 (en) 2013-05-17 2017-03-07 Microcontinuum, Inc. Tools and methods for producing nanoantenna electronic devices
TWI664066B (zh) * 2014-09-30 2019-07-01 日商富士軟片股份有限公司 多孔質體的製造方法、元件的製造方法、配線結構的製造方法
US10892167B2 (en) * 2019-03-05 2021-01-12 Canon Kabushiki Kaisha Gas permeable superstrate and methods of using the same
FR3108780B1 (fr) * 2020-03-30 2022-03-18 Commissariat Energie Atomique Procédé de réalisation d’une zone d’individualisation d’un circuit intégré

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JPS613339A (ja) * 1984-06-18 1986-01-09 Hitachi Ltd 高密度情報記録円板複製用スタンパおよびその製造方法
JPH03100942A (ja) * 1989-09-13 1991-04-25 Hitachi Chem Co Ltd 光ディスク用スタンパの製造方法
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Also Published As

Publication number Publication date
TWI313490B (en) 2009-08-11
KR100791443B1 (ko) 2008-01-10
WO2005031855A1 (en) 2005-04-07
JP4726789B2 (ja) 2011-07-20
US7446057B2 (en) 2008-11-04
DE602004024585D1 (de) 2010-01-21
EP1702359A1 (de) 2006-09-20
EP1702359B1 (de) 2009-12-09
US20070275556A1 (en) 2007-11-29
KR20060086354A (ko) 2006-07-31
CN100483672C (zh) 2009-04-29
JP2007507860A (ja) 2007-03-29
TW200512832A (en) 2005-04-01
CN1860605A (zh) 2006-11-08

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