DE60234653D1 - Programmierbare Hochgeschwindigkeits-E/A-Schnittstelle - Google Patents

Programmierbare Hochgeschwindigkeits-E/A-Schnittstelle

Info

Publication number
DE60234653D1
DE60234653D1 DE60234653T DE60234653T DE60234653D1 DE 60234653 D1 DE60234653 D1 DE 60234653D1 DE 60234653 T DE60234653 T DE 60234653T DE 60234653 T DE60234653 T DE 60234653T DE 60234653 D1 DE60234653 D1 DE 60234653D1
Authority
DE
Germany
Prior art keywords
interface
speed
programmable high
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60234653T
Other languages
English (en)
Inventor
Bonnie I Wang
Chiakang Sung
Joseph Huang
Khai Nguyen
Philip Pan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of DE60234653D1 publication Critical patent/DE60234653D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017581—Coupling arrangements; Interface arrangements programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17788—Structural details for adapting physical parameters for input/output [I/O] voltages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Microcomputers (AREA)
DE60234653T 2001-08-29 2002-08-28 Programmierbare Hochgeschwindigkeits-E/A-Schnittstelle Expired - Lifetime DE60234653D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31590401P 2001-08-29 2001-08-29
US10/229,342 US6825698B2 (en) 2001-08-29 2002-08-26 Programmable high speed I/O interface

Publications (1)

Publication Number Publication Date
DE60234653D1 true DE60234653D1 (de) 2010-01-14

Family

ID=26923211

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60234653T Expired - Lifetime DE60234653D1 (de) 2001-08-29 2002-08-28 Programmierbare Hochgeschwindigkeits-E/A-Schnittstelle
DE60222513T Expired - Lifetime DE60222513T2 (de) 2001-08-29 2002-08-28 Programmierbare schnelle Eingangs-/Ausgangsschnittstelle

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60222513T Expired - Lifetime DE60222513T2 (de) 2001-08-29 2002-08-28 Programmierbare schnelle Eingangs-/Ausgangsschnittstelle

Country Status (4)

Country Link
US (10) US6825698B2 (de)
EP (2) EP1294099B1 (de)
JP (9) JP2003157229A (de)
DE (2) DE60234653D1 (de)

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Also Published As

Publication number Publication date
EP1294099B1 (de) 2007-09-19
US7315188B2 (en) 2008-01-01
US20050134332A1 (en) 2005-06-23
US20130278290A1 (en) 2013-10-24
JP5268195B2 (ja) 2013-08-21
JP6073278B2 (ja) 2017-02-01
US20030042941A1 (en) 2003-03-06
US8487665B2 (en) 2013-07-16
JP2003157229A (ja) 2003-05-30
JP2016173866A (ja) 2016-09-29
US20060220703A1 (en) 2006-10-05
DE60222513D1 (de) 2007-10-31
US7586341B2 (en) 2009-09-08
EP2226941B1 (de) 2015-09-16
EP1294099A2 (de) 2003-03-19
JP2011165214A (ja) 2011-08-25
US20100045349A1 (en) 2010-02-25
JP2008217810A (ja) 2008-09-18
US8829948B2 (en) 2014-09-09
US20140340125A1 (en) 2014-11-20
US20110227606A1 (en) 2011-09-22
US9473145B2 (en) 2016-10-18
US7116135B2 (en) 2006-10-03
JP2015043230A (ja) 2015-03-05
US20170005662A1 (en) 2017-01-05
EP2226941A3 (de) 2014-05-07
EP1294099A3 (de) 2004-03-17
JP2006236386A (ja) 2006-09-07
US20080186056A1 (en) 2008-08-07
JP2010141901A (ja) 2010-06-24
DE60222513T2 (de) 2008-06-26
EP2226941A2 (de) 2010-09-08
US6825698B2 (en) 2004-11-30
JP2015043229A (ja) 2015-03-05
US20170005661A1 (en) 2017-01-05
JP2013214332A (ja) 2013-10-17

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