DE60004124D1 - Halbleiterspeicheranordnungen und ihre Betriebsverfahren - Google Patents

Halbleiterspeicheranordnungen und ihre Betriebsverfahren

Info

Publication number
DE60004124D1
DE60004124D1 DE60004124T DE60004124T DE60004124D1 DE 60004124 D1 DE60004124 D1 DE 60004124D1 DE 60004124 T DE60004124 T DE 60004124T DE 60004124 T DE60004124 T DE 60004124T DE 60004124 D1 DE60004124 D1 DE 60004124D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory devices
operating methods
operating
methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60004124T
Other languages
English (en)
Other versions
DE60004124T2 (de
Inventor
Takaaki Suzuki
Toshiya Uchida
Kotoku Sato
Yoshimasa Yagishita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60004124D1 publication Critical patent/DE60004124D1/de
Publication of DE60004124T2 publication Critical patent/DE60004124T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
DE60004124T 1999-05-07 2000-05-05 Halbleiterspeicheranordnungen und ihre Betriebsverfahren Expired - Lifetime DE60004124T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP12671699 1999-05-07
JP12671699 1999-05-07
JP2000076045A JP4034923B2 (ja) 1999-05-07 2000-03-17 半導体記憶装置の動作制御方法および半導体記憶装置
JP2000076045 2000-03-17

Publications (2)

Publication Number Publication Date
DE60004124D1 true DE60004124D1 (de) 2003-09-04
DE60004124T2 DE60004124T2 (de) 2004-03-11

Family

ID=26462846

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60004124T Expired - Lifetime DE60004124T2 (de) 1999-05-07 2000-05-05 Halbleiterspeicheranordnungen und ihre Betriebsverfahren

Country Status (6)

Country Link
US (1) US6629224B1 (de)
EP (1) EP1050882B1 (de)
JP (1) JP4034923B2 (de)
KR (1) KR100617334B1 (de)
DE (1) DE60004124T2 (de)
TW (1) TW454337B (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035153A (ja) * 1999-07-23 2001-02-09 Fujitsu Ltd 半導体記憶装置
JP2002245778A (ja) * 2001-02-16 2002-08-30 Fujitsu Ltd 半導体装置
US7003643B1 (en) 2001-04-16 2006-02-21 Micron Technology, Inc. Burst counter controller and method in a memory device operable in a 2-bit prefetch mode
JP2002352576A (ja) 2001-05-24 2002-12-06 Nec Corp 半導体記憶装置
JP2002358231A (ja) * 2001-05-31 2002-12-13 Fujitsu Ltd メモリ制御システム
JP4731730B2 (ja) * 2001-06-04 2011-07-27 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4768163B2 (ja) * 2001-08-03 2011-09-07 富士通セミコンダクター株式会社 半導体メモリ
JP2005514723A (ja) * 2002-01-11 2005-05-19 株式会社ハイニックスセミコンダクター 半導体メモリ装置のリフレッシュ周期増大方法
US6671212B2 (en) 2002-02-08 2003-12-30 Ati Technologies Inc. Method and apparatus for data inversion in memory device
US6728150B2 (en) 2002-02-11 2004-04-27 Micron Technology, Inc. Method and apparatus for supplementary command bus
JP3792602B2 (ja) * 2002-05-29 2006-07-05 エルピーダメモリ株式会社 半導体記憶装置
JP4077295B2 (ja) * 2002-10-23 2008-04-16 株式会社東芝 同期型半導体記憶装置及びその動作方法
US7042777B2 (en) * 2004-01-28 2006-05-09 Infineon Technologies Ag Memory device with non-variable write latency
JP4615896B2 (ja) 2004-05-25 2011-01-19 富士通セミコンダクター株式会社 半導体記憶装置および該半導体記憶装置の制御方法
JP2006059046A (ja) 2004-08-19 2006-03-02 Nec Computertechno Ltd メモリの制御方式およびメモリ制御回路
WO2006080063A1 (ja) * 2005-01-27 2006-08-03 Spansion Llc 半導体装置、アドレス割り付け方法及びベリファイ方法
US7757061B2 (en) * 2005-05-03 2010-07-13 Micron Technology, Inc. System and method for decoding commands based on command signals and operating state
KR100732241B1 (ko) * 2006-01-24 2007-06-27 삼성전자주식회사 테스트 효율이 높은 반도체 메모리 장치, 반도체 메모리장치의 테스트 방법, 및 이를 구비한 테스트 시스템
US8296497B2 (en) * 2006-03-14 2012-10-23 Stmicroelectronics Pvt. Ltd. Self-updating memory controller
JP4267006B2 (ja) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 半導体記憶装置
JP2008097663A (ja) 2006-10-06 2008-04-24 Sony Corp 半導体記憶装置
US7405992B2 (en) * 2006-10-25 2008-07-29 Qimonda North America Corp. Method and apparatus for communicating command and address signals
KR100909965B1 (ko) * 2007-05-23 2009-07-29 삼성전자주식회사 버스를 공유하는 휘발성 메모리 및 불휘발성 메모리를구비하는 반도체 메모리 시스템 및 불휘발성 메모리의 동작제어 방법
US20090021995A1 (en) * 2007-07-19 2009-01-22 Jong-Hoon Oh Early Write Method and Apparatus
JP2012038377A (ja) * 2010-08-05 2012-02-23 Elpida Memory Inc 半導体装置及びその試験方法
US8775725B2 (en) 2010-12-06 2014-07-08 Intel Corporation Memory device refresh commands on the fly
KR101198141B1 (ko) * 2010-12-21 2012-11-12 에스케이하이닉스 주식회사 반도체 메모리 장치
DE112011105984T5 (de) 2011-12-20 2014-09-18 Intel Corporation Dynamische teilweise Abschaltung eines arbeitsspeicherseitigen Zwischenspeichers in einer Arbeitsspeicherhierarchie auf zwei Ebenen
KR101980162B1 (ko) * 2012-06-28 2019-08-28 에스케이하이닉스 주식회사 메모리
US9740485B2 (en) 2012-10-26 2017-08-22 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9754648B2 (en) 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9734097B2 (en) * 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US9563565B2 (en) 2013-08-14 2017-02-07 Micron Technology, Inc. Apparatuses and methods for providing data from a buffer
US10365835B2 (en) 2014-05-28 2019-07-30 Micron Technology, Inc. Apparatuses and methods for performing write count threshold wear leveling operations
KR102561095B1 (ko) * 2016-04-14 2023-07-31 에스케이하이닉스 주식회사 반도체 메모리 장치의 동작 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053990A (en) 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US5749086A (en) 1996-02-29 1998-05-05 Micron Technology, Inc. Simplified clocked DRAM with a fast command input
JP4017248B2 (ja) * 1998-04-10 2007-12-05 株式会社日立製作所 半導体装置
JP4226686B2 (ja) * 1998-05-07 2009-02-18 株式会社東芝 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ
US6295231B1 (en) * 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
JP4260247B2 (ja) * 1998-09-02 2009-04-30 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
JP2000100156A (ja) * 1998-09-25 2000-04-07 Fujitsu Ltd 半導体記憶装置のセル情報書き込み方法及び半導体記憶装置
JP2000163961A (ja) * 1998-11-26 2000-06-16 Mitsubishi Electric Corp 同期型半導体集積回路装置
JP2002093167A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR20010020813A (ko) 2001-03-15
EP1050882A3 (de) 2001-08-16
JP2001028190A (ja) 2001-01-30
KR100617334B1 (ko) 2006-08-31
EP1050882B1 (de) 2003-07-30
JP4034923B2 (ja) 2008-01-16
DE60004124T2 (de) 2004-03-11
TW454337B (en) 2001-09-11
US6629224B1 (en) 2003-09-30
EP1050882A2 (de) 2000-11-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE