DE60141670D1 - Halbleiterspeicherbauelement, dessen Herstellungsverfahren und dessen Betriebsweise - Google Patents

Halbleiterspeicherbauelement, dessen Herstellungsverfahren und dessen Betriebsweise

Info

Publication number
DE60141670D1
DE60141670D1 DE60141670T DE60141670T DE60141670D1 DE 60141670 D1 DE60141670 D1 DE 60141670D1 DE 60141670 T DE60141670 T DE 60141670T DE 60141670 T DE60141670 T DE 60141670T DE 60141670 D1 DE60141670 D1 DE 60141670D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60141670T
Other languages
English (en)
Inventor
Takashi Miida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innotech Corp
Original Assignee
Innotech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001114291A external-priority patent/JP3283872B1/ja
Priority claimed from JP2001123213A external-priority patent/JP3249811B1/ja
Priority claimed from JP2001143920A external-priority patent/JP3249812B1/ja
Application filed by Innotech Corp filed Critical Innotech Corp
Application granted granted Critical
Publication of DE60141670D1 publication Critical patent/DE60141670D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
DE60141670T 2000-11-09 2001-10-31 Halbleiterspeicherbauelement, dessen Herstellungsverfahren und dessen Betriebsweise Expired - Lifetime DE60141670D1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000342616 2000-11-09
JP2001114291A JP3283872B1 (ja) 2001-04-12 2001-04-12 半導体記憶装置、その製造方法及び半導体記憶装置の駆動方法
JP2001123213A JP3249811B1 (ja) 2000-11-09 2001-04-20 半導体記憶装置、その製造方法及び半導体記憶装置の駆動方法
JP2001143920A JP3249812B1 (ja) 2001-05-14 2001-05-14 半導体記憶装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE60141670D1 true DE60141670D1 (de) 2010-05-12

Family

ID=27481764

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60141670T Expired - Lifetime DE60141670D1 (de) 2000-11-09 2001-10-31 Halbleiterspeicherbauelement, dessen Herstellungsverfahren und dessen Betriebsweise

Country Status (6)

Country Link
US (1) US6538925B2 (de)
EP (1) EP1205978B1 (de)
KR (1) KR100441788B1 (de)
CN (1) CN1162913C (de)
DE (1) DE60141670D1 (de)
TW (1) TW511280B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4191975B2 (ja) * 2001-11-01 2008-12-03 イノテック株式会社 トランジスタとそれを用いた半導体メモリ、およびトランジスタの製造方法
JP2004072060A (ja) 2001-11-22 2004-03-04 Innotech Corp トランジスタとそれを用いた半導体メモリ、およびトランジスタの駆動方法
US6795342B1 (en) * 2002-12-02 2004-09-21 Advanced Micro Devices, Inc. System for programming a non-volatile memory cell
JP2004214495A (ja) * 2003-01-07 2004-07-29 Innotech Corp トランジスタとそれを用いた半導体メモリ、および半導体メモリの製造方法
JP4557678B2 (ja) * 2004-02-13 2010-10-06 イノテック株式会社 半導体記憶装置
KR100598049B1 (ko) * 2004-10-28 2006-07-07 삼성전자주식회사 멀티 비트 비휘발성 메모리 셀을 포함하는 반도체 소자 및그 제조 방법
US7193900B2 (en) * 2005-01-18 2007-03-20 Mammen Thomas CACT-TG (CATT) low voltage NVM cells
TWI277205B (en) * 2005-10-05 2007-03-21 Promos Technologies Inc Flash memory structure and method for fabricating the same
KR100724560B1 (ko) * 2005-11-18 2007-06-04 삼성전자주식회사 결정질 반도체층을 갖는 반도체소자, 그의 제조방법 및그의 구동방법
US9159568B2 (en) 2006-02-04 2015-10-13 Cypress Semiconductor Corporation Method for fabricating memory cells having split charge storage nodes
US8742486B2 (en) * 2006-02-04 2014-06-03 Spansion, Llc Flash memory cells having trenched storage elements
WO2007089949A2 (en) * 2006-02-04 2007-08-09 Spansion Llc Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes
US7394702B2 (en) 2006-04-05 2008-07-01 Spansion Llc Methods for erasing and programming memory devices
US20070247924A1 (en) * 2006-04-06 2007-10-25 Wei Zheng Methods for erasing memory devices and multi-level programming memory device
CN103794610B (zh) * 2014-01-28 2016-08-17 北京芯盈速腾电子科技有限责任公司 非挥发性内存单元及其制造方法
CN103811498B (zh) * 2014-02-25 2023-08-18 北京芯盈速腾电子科技有限责任公司 一种低电场源极抹除非挥发性内存单元及其制造方法
US20170345834A1 (en) * 2016-05-25 2017-11-30 Globalfoundries Inc. Soi memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380057A (en) * 1980-10-27 1983-04-12 International Business Machines Corporation Electrically alterable double dense memory
DE69316298T2 (de) * 1992-10-02 1998-04-23 Matsushita Electric Ind Co Ltd Nichtflüchtige Speicherzelle
DE19612676C2 (de) * 1996-03-29 2002-06-06 Infineon Technologies Ag Anordnung von Halbleiter-Speicherzellen mit zwei Floating-Gates in einem Zellenfeld und Verfahren zum Betrieb einer nichtflüchtigen Halbleiter-Speicherzelle
JP3253552B2 (ja) * 1996-05-31 2002-02-04 三洋電機株式会社 半導体装置の製造方法
US5949711A (en) 1996-09-26 1999-09-07 Waferscale Integration, Inc. Dual bit memory cell
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
JP3070531B2 (ja) * 1997-06-27 2000-07-31 日本電気株式会社 不揮発性半導体記憶装置
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

Also Published As

Publication number Publication date
KR20020036731A (ko) 2002-05-16
CN1363956A (zh) 2002-08-14
EP1205978A2 (de) 2002-05-15
KR100441788B1 (ko) 2004-07-27
TW511280B (en) 2002-11-21
US20020054512A1 (en) 2002-05-09
CN1162913C (zh) 2004-08-18
EP1205978B1 (de) 2010-03-31
EP1205978A3 (de) 2003-06-25
US6538925B2 (en) 2003-03-25

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