DE3841927C2 - - Google Patents

Info

Publication number
DE3841927C2
DE3841927C2 DE3841927A DE3841927A DE3841927C2 DE 3841927 C2 DE3841927 C2 DE 3841927C2 DE 3841927 A DE3841927 A DE 3841927A DE 3841927 A DE3841927 A DE 3841927A DE 3841927 C2 DE3841927 C2 DE 3841927C2
Authority
DE
Germany
Prior art keywords
polycrystalline silicon
silicon layer
semiconductor
implantation
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3841927A
Other languages
German (de)
English (en)
Other versions
DE3841927A1 (de
Inventor
Yoshinori Itami Hyogo Jp Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3841927A1 publication Critical patent/DE3841927A1/de
Application granted granted Critical
Publication of DE3841927C2 publication Critical patent/DE3841927C2/de
Granted legal-status Critical Current

Links

Classifications

    • H10P30/20—
    • H10P32/302—
    • H10D64/011—
    • H10D64/0113—
    • H10P32/1414—
    • H10P32/171—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
DE3841927A 1987-12-14 1988-12-13 Verfahren zur herstellung einer halbleitervorrichtung mit einem elektrischen kontakt Granted DE3841927A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62317808A JPH0750696B2 (ja) 1987-12-14 1987-12-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3841927A1 DE3841927A1 (de) 1989-06-22
DE3841927C2 true DE3841927C2 (cg-RX-API-DMAC10.html) 1991-11-21

Family

ID=18092271

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3841927A Granted DE3841927A1 (de) 1987-12-14 1988-12-13 Verfahren zur herstellung einer halbleitervorrichtung mit einem elektrischen kontakt

Country Status (4)

Country Link
US (1) US4906591A (cg-RX-API-DMAC10.html)
JP (1) JPH0750696B2 (cg-RX-API-DMAC10.html)
KR (1) KR920004175B1 (cg-RX-API-DMAC10.html)
DE (1) DE3841927A1 (cg-RX-API-DMAC10.html)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2954263B2 (ja) * 1990-03-22 1999-09-27 沖電気工業株式会社 半導体装置の製造方法
KR930000581B1 (ko) * 1990-04-04 1993-01-25 금성일렉트론 주식회사 자기 정렬된 캐패시터 콘택을 갖는 셀 제조방법 및 구조
JP2720592B2 (ja) * 1990-09-25 1998-03-04 日本電気株式会社 半導体装置の製造方法
DE4331549A1 (de) * 1993-09-16 1995-04-13 Gold Star Electronics Verfahren zur Herstellung einer ULSI-Halbleitereinrichtung
KR0166824B1 (ko) * 1995-12-19 1999-02-01 문정환 반도체 소자의 제조방법
US6017829A (en) 1997-04-01 2000-01-25 Micron Technology, Inc. Implanted conductor and methods of making
US5998294A (en) * 1998-04-29 1999-12-07 The United States Of America As Represented By The Secretary Of The Navy Method for forming improved electrical contacts on non-planar structures
US6187481B1 (en) * 1998-08-20 2001-02-13 Micron Technology, Inc. Semiconductive material stencil mask and methods of manufacturing stencil masks from semiconductive material, utilizing different dopants
US6300017B1 (en) * 1998-08-20 2001-10-09 Micron Technology, Inc. Stencil masks and methods of manufacturing stencil masks
DE10149199B4 (de) * 2001-10-05 2006-05-18 Infineon Technologies Ag Speicherzellenfeld und Verfahren zu seiner Herstellung
KR100905872B1 (ko) * 2007-08-24 2009-07-03 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법
JP2017168698A (ja) * 2016-03-17 2017-09-21 東芝メモリ株式会社 半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871067A (en) * 1973-06-29 1975-03-18 Ibm Method of manufacturing a semiconductor device
JPS54128668A (en) * 1978-03-30 1979-10-05 Toshiba Corp Manufacture for electronic component device
US4502206A (en) * 1983-11-18 1985-03-05 Rca Corporation Method of forming semiconductor contacts by implanting ions of neutral species at the interfacial region
US4693925A (en) * 1984-03-01 1987-09-15 Advanced Micro Devices, Inc. Integrated circuit structure having intermediate metal silicide layer
JPS6246575A (ja) * 1985-08-23 1987-02-28 Sharp Corp 薄膜半導体装置

Also Published As

Publication number Publication date
JPH0750696B2 (ja) 1995-05-31
JPH01157522A (ja) 1989-06-20
DE3841927A1 (de) 1989-06-22
KR890011033A (ko) 1989-08-12
KR920004175B1 (ko) 1992-05-30
US4906591A (en) 1990-03-06

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee