DE69031543T2 - Verfahren zum Herstellen einer Halbleitervorrichtung - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung

Info

Publication number
DE69031543T2
DE69031543T2 DE69031543T DE69031543T DE69031543T2 DE 69031543 T2 DE69031543 T2 DE 69031543T2 DE 69031543 T DE69031543 T DE 69031543T DE 69031543 T DE69031543 T DE 69031543T DE 69031543 T2 DE69031543 T2 DE 69031543T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031543T
Other languages
English (en)
Other versions
DE69031543D1 (de
Inventor
Hideto Ozaki
Shuichi Mayumi
Seiji Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE69031543D1 publication Critical patent/DE69031543D1/de
Publication of DE69031543T2 publication Critical patent/DE69031543T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69031543T 1989-02-17 1990-02-15 Verfahren zum Herstellen einer Halbleitervorrichtung Expired - Fee Related DE69031543T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3863889 1989-02-17

Publications (2)

Publication Number Publication Date
DE69031543D1 DE69031543D1 (de) 1997-11-13
DE69031543T2 true DE69031543T2 (de) 1998-04-09

Family

ID=12530785

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031543T Expired - Fee Related DE69031543T2 (de) 1989-02-17 1990-02-15 Verfahren zum Herstellen einer Halbleitervorrichtung

Country Status (3)

Country Link
US (1) US5084416A (de)
EP (1) EP0383610B1 (de)
DE (1) DE69031543T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2598328B2 (ja) * 1989-10-17 1997-04-09 三菱電機株式会社 半導体装置およびその製造方法
US5177589A (en) * 1990-01-29 1993-01-05 Hitachi, Ltd. Refractory metal thin film having a particular step coverage factor and ratio of surface roughness
US5279990A (en) * 1990-03-02 1994-01-18 Motorola, Inc. Method of making a small geometry contact using sidewall spacers
JP3074713B2 (ja) * 1990-09-18 2000-08-07 日本電気株式会社 半導体装置の製造方法
JP2616227B2 (ja) * 1990-11-24 1997-06-04 日本電気株式会社 半導体装置
KR940000504B1 (ko) * 1991-03-20 1994-01-21 삼성전자 주식회사 반도체장치의 층간콘택구조 및 그 제조방법
JP3271272B2 (ja) * 1991-11-12 2002-04-02 日本電気株式会社 半導体装置の製造方法
JP2875093B2 (ja) * 1992-03-17 1999-03-24 三菱電機株式会社 半導体装置
US5328553A (en) * 1993-02-02 1994-07-12 Motorola Inc. Method for fabricating a semiconductor device having a planar surface
US5308777A (en) * 1993-07-28 1994-05-03 United Microelectronics Corporation Mask ROM process
US5449644A (en) * 1994-01-13 1995-09-12 United Microelectronics Corporation Process for contact hole formation using a sacrificial SOG layer
US5471094A (en) * 1994-02-24 1995-11-28 Integrated Device Technology, Inc. Self-aligned via structure
US6153501A (en) 1998-05-19 2000-11-28 Micron Technology, Inc. Method of reducing overetch during the formation of a semiconductor device
US5498570A (en) * 1994-09-15 1996-03-12 Micron Technology Inc. Method of reducing overetch during the formation of a semiconductor device
US5578873A (en) * 1994-10-12 1996-11-26 Micron Technology, Inc. Integrated circuitry having a thin film polysilicon layer in ohmic contact with a conductive layer
US5874359A (en) * 1995-04-27 1999-02-23 Industrial Technology Research Institute Small contacts for ultra large scale integration semiconductor devices without separation ground rule
US5895766A (en) * 1995-09-20 1999-04-20 Micron Technology, Inc. Method of forming a field effect transistor
TW305069B (en) * 1996-05-06 1997-05-11 United Microelectronics Corp The IC pad structure and its manufacturing method
JP3665426B2 (ja) * 1996-07-17 2005-06-29 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法
US6051501A (en) * 1996-10-09 2000-04-18 Micron Technology, Inc. Method of reducing overetch during the formation of a semiconductor device
KR100224720B1 (ko) * 1996-10-31 1999-10-15 윤종용 반도체장치의 콘택홀 형성방법
US6214727B1 (en) * 1997-02-11 2001-04-10 Micron Technology, Inc. Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry
JP3120750B2 (ja) * 1997-03-14 2000-12-25 日本電気株式会社 半導体装置およびその製造方法
TW396646B (en) * 1997-09-11 2000-07-01 Lg Semicon Co Ltd Manufacturing method of semiconductor devices
US6229174B1 (en) * 1997-12-08 2001-05-08 Micron Technology, Inc. Contact structure for memory device
KR100280809B1 (ko) * 1998-12-30 2001-03-02 김영환 반도체 소자의 접합부 형성 방법
DE102010029533B3 (de) 2010-05-31 2012-02-09 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Selektive Größenreduzierung von Kontaktelementen in einem Halbleiterbauelement
CN105097649B (zh) * 2014-05-04 2017-11-03 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US10052875B1 (en) * 2017-02-23 2018-08-21 Fujifilm Dimatix, Inc. Reducing size variations in funnel nozzles
CN111128872B (zh) * 2019-12-30 2022-11-25 上海集成电路研发中心有限公司 一种接触孔及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3922184A (en) * 1973-12-26 1975-11-25 Ibm Method for forming openings through insulative layers in the fabrication of integrated circuits
JPS534475A (en) * 1976-07-02 1978-01-17 Hitachi Ltd Etching method
JPS5534444A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
JPS5617040A (en) * 1979-07-20 1981-02-18 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS59104125A (ja) * 1982-12-06 1984-06-15 Nec Corp 半導体装置の製造方法
JPS59184548A (ja) * 1983-04-05 1984-10-19 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4502209A (en) * 1983-08-31 1985-03-05 At&T Bell Laboratories Forming low-resistance contact to silicon
JPS6146063A (ja) * 1984-08-10 1986-03-06 Hitachi Ltd 半導体装置の製造方法
FR2588417B1 (fr) * 1985-10-03 1988-07-29 Bull Sa Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant
JPS63265431A (ja) * 1987-04-22 1988-11-01 Mitsubishi Electric Corp 半導体装置
JPH0834311B2 (ja) * 1987-06-10 1996-03-29 日本電装株式会社 半導体装置の製造方法
KR920009718B1 (ko) * 1987-08-10 1992-10-22 스미도모덴기고오교오 가부시기가이샤 화합물반도체장치 및 그 제조방법

Also Published As

Publication number Publication date
US5084416A (en) 1992-01-28
EP0383610A3 (de) 1994-09-14
DE69031543D1 (de) 1997-11-13
EP0383610B1 (de) 1997-10-08
EP0383610A2 (de) 1990-08-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA,

8339 Ceased/non-payment of the annual fee