DE3705152A1 - Halbleitereinrichtung und verfahren zu deren herstellung - Google Patents

Halbleitereinrichtung und verfahren zu deren herstellung

Info

Publication number
DE3705152A1
DE3705152A1 DE19873705152 DE3705152A DE3705152A1 DE 3705152 A1 DE3705152 A1 DE 3705152A1 DE 19873705152 DE19873705152 DE 19873705152 DE 3705152 A DE3705152 A DE 3705152A DE 3705152 A1 DE3705152 A1 DE 3705152A1
Authority
DE
Germany
Prior art keywords
thin
layer
connection layer
area
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873705152
Other languages
German (de)
English (en)
Other versions
DE3705152C2 (enExample
Inventor
Hiroshi Mochizuki
Reiji Tamaki
Junichi Arima
Masaaki Ikegami
Eisuke Tanaka
Kenji Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3705152A1 publication Critical patent/DE3705152A1/de
Application granted granted Critical
Publication of DE3705152C2 publication Critical patent/DE3705152C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6314—Formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/065—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by making at least a portion of the conductive part non-conductive, e.g. by oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19873705152 1986-02-20 1987-02-18 Halbleitereinrichtung und verfahren zu deren herstellung Granted DE3705152A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61037785A JPS62194644A (ja) 1986-02-20 1986-02-20 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE3705152A1 true DE3705152A1 (de) 1987-08-27
DE3705152C2 DE3705152C2 (enExample) 1989-07-20

Family

ID=12507140

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873705152 Granted DE3705152A1 (de) 1986-02-20 1987-02-18 Halbleitereinrichtung und verfahren zu deren herstellung

Country Status (4)

Country Link
US (1) US4884120A (enExample)
JP (1) JPS62194644A (enExample)
KR (1) KR900007757B1 (enExample)
DE (1) DE3705152A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4140330C1 (enExample) * 1991-12-06 1993-03-18 Texas Instruments Deutschland Gmbh, 8050 Freising, De

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482547A (en) * 1987-09-24 1989-03-28 Tadahiro Omi Semiconductor device
US5252382A (en) * 1991-09-03 1993-10-12 Cornell Research Foundation, Inc. Interconnect structures having patterned interfaces to minimize stress migration and related electromigration damages
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5783483A (en) * 1993-02-24 1998-07-21 Intel Corporation Method of fabricating a barrier against metal diffusion
US5897376A (en) * 1993-09-20 1999-04-27 Seiko Instruments Inc. Method of manufacturing a semiconductor device having a reflection reducing film
US5439731A (en) * 1994-03-11 1995-08-08 Cornell Research Goundation, Inc. Interconnect structures containing blocked segments to minimize stress migration and electromigration damage
JPH09205185A (ja) 1996-01-26 1997-08-05 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
EP4541394A3 (en) 2016-10-21 2025-07-09 Sanofi-Aventis Deutschland GmbH Liquid medicament administration device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3866311A (en) * 1971-06-14 1975-02-18 Nat Semiconductor Corp Method of providing electrically isolated overlapping metallic conductors
DE3109801A1 (de) * 1981-03-13 1982-09-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleiterbauelementen
EP0216017A2 (en) * 1985-06-06 1987-04-01 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including forming a multi-level interconnection layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5955037A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体装置
GB8316477D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
JPS60234346A (ja) * 1984-05-07 1985-11-21 Nec Corp 半導体装置
US4707457A (en) * 1986-04-03 1987-11-17 Advanced Micro Devices, Inc. Method for making improved contact for integrated circuit structure
JP3480738B2 (ja) * 1992-06-23 2003-12-22 株式会社東芝 情報処理装置における表示方法及び情報処理装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3866311A (en) * 1971-06-14 1975-02-18 Nat Semiconductor Corp Method of providing electrically isolated overlapping metallic conductors
DE3109801A1 (de) * 1981-03-13 1982-09-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleiterbauelementen
EP0216017A2 (en) * 1985-06-06 1987-04-01 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including forming a multi-level interconnection layer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Cadien, K.C. and Losee, D.L.: A method for eleminating hillocks in Integrated-circuit metallizations In: Journal of Vacuum Science and Technology, B2 (1), Jan.-März 1984, S. 82-83 *
J-PS Abstract E-385, 4.März 1986, Bd. 10, Nr. 54 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4140330C1 (enExample) * 1991-12-06 1993-03-18 Texas Instruments Deutschland Gmbh, 8050 Freising, De

Also Published As

Publication number Publication date
KR870008388A (ko) 1987-09-26
JPS62194644A (ja) 1987-08-27
US4884120A (en) 1989-11-28
KR900007757B1 (ko) 1990-10-19
DE3705152C2 (enExample) 1989-07-20

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee