DE3872803T2 - Selbstjustierende metallisierung einer halbleiteranordnung und verfahren zur selektiven wolframabscheidung. - Google Patents
Selbstjustierende metallisierung einer halbleiteranordnung und verfahren zur selektiven wolframabscheidung.Info
- Publication number
- DE3872803T2 DE3872803T2 DE8888201742T DE3872803T DE3872803T2 DE 3872803 T2 DE3872803 T2 DE 3872803T2 DE 8888201742 T DE8888201742 T DE 8888201742T DE 3872803 T DE3872803 T DE 3872803T DE 3872803 T2 DE3872803 T2 DE 3872803T2
- Authority
- DE
- Germany
- Prior art keywords
- metalization
- self
- adjusting
- semiconductor arrangement
- tungsten deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000151 deposition Methods 0.000 title 1
- 230000008021 deposition Effects 0.000 title 1
- 238000001465 metallisation Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title 1
- 229910052721 tungsten Inorganic materials 0.000 title 1
- 239000010937 tungsten Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/903—Catalyst aided deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/090,301 US4822749A (en) | 1987-08-27 | 1987-08-27 | Self-aligned metallization for semiconductor device and process using selectively deposited tungsten |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3872803D1 DE3872803D1 (de) | 1992-08-20 |
DE3872803T2 true DE3872803T2 (de) | 1993-02-18 |
Family
ID=22222186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8888201742T Expired - Fee Related DE3872803T2 (de) | 1987-08-27 | 1988-08-16 | Selbstjustierende metallisierung einer halbleiteranordnung und verfahren zur selektiven wolframabscheidung. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4822749A (de) |
EP (1) | EP0307021B1 (de) |
JP (1) | JP2598481B2 (de) |
KR (1) | KR970011263B1 (de) |
DE (1) | DE3872803T2 (de) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4994402A (en) * | 1987-06-26 | 1991-02-19 | Hewlett-Packard Company | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
US4985371A (en) * | 1988-12-09 | 1991-01-15 | At&T Bell Laboratories | Process for making integrated-circuit device metallization |
US5358902A (en) * | 1989-06-26 | 1994-10-25 | U.S. Philips Corporation | Method of producing conductive pillars in semiconductor device |
GB2233820A (en) * | 1989-06-26 | 1991-01-16 | Philips Nv | Providing an electrode on a semiconductor device |
JPH03141645A (ja) * | 1989-07-10 | 1991-06-17 | Texas Instr Inc <Ti> | ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子 |
US4933303A (en) * | 1989-07-25 | 1990-06-12 | Standard Microsystems Corporation | Method of making self-aligned tungsten interconnection in an integrated circuit |
US4935376A (en) * | 1989-10-12 | 1990-06-19 | At&T Bell Laboratories | Making silicide gate level runners |
US5070029A (en) * | 1989-10-30 | 1991-12-03 | Motorola, Inc. | Semiconductor process using selective deposition |
US4987099A (en) * | 1989-12-29 | 1991-01-22 | North American Philips Corp. | Method for selectively filling contacts or vias or various depths with CVD tungsten |
US5483104A (en) * | 1990-01-12 | 1996-01-09 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US5166771A (en) * | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US5118639A (en) * | 1990-05-29 | 1992-06-02 | Motorola, Inc. | Process for the formation of elevated source and drain structures in a semiconductor device |
US5156994A (en) * | 1990-12-21 | 1992-10-20 | Texas Instruments Incorporated | Local interconnect method and structure |
US5115296A (en) * | 1991-01-14 | 1992-05-19 | United Microelectronics Corporation | Preferential oxidization self-aligned contact technology |
US5280190A (en) * | 1991-03-21 | 1994-01-18 | Industrial Technology Research Institute | Self aligned emitter/runner integrated circuit |
US5313084A (en) * | 1992-05-29 | 1994-05-17 | Sgs-Thomson Microelectronics, Inc. | Interconnect structure for an integrated circuit |
DE4339919C2 (de) * | 1993-11-23 | 1999-03-04 | Siemens Ag | Herstellverfahren für eine aus Silizid bestehende Anschlußfläche für ein Siliziumgebiet |
US5945738A (en) * | 1994-05-31 | 1999-08-31 | Stmicroelectronics, Inc. | Dual landing pad structure in an integrated circuit |
US5702979A (en) * | 1994-05-31 | 1997-12-30 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
US5956615A (en) * | 1994-05-31 | 1999-09-21 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
FR2728390A1 (fr) * | 1994-12-19 | 1996-06-21 | Korea Electronics Telecomm | Procede de formation d'un transistor a film mince |
US5705427A (en) * | 1994-12-22 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
JP4156044B2 (ja) * | 1994-12-22 | 2008-09-24 | エスティーマイクロエレクトロニクス,インコーポレイテッド | 集積回路におけるランディングパッド構成体の製造方法 |
US5480830A (en) * | 1995-04-04 | 1996-01-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making depleted gate transistor for high voltage operation |
US5654860A (en) * | 1995-08-16 | 1997-08-05 | Micron Technology, Inc. | Well resistor for ESD protection of CMOS circuits |
KR100298819B1 (ko) | 1995-11-30 | 2001-11-02 | 로데릭 더블류 루이스 | 반도체칩에서의정전기방전(esd)보호구조 |
US6507074B2 (en) | 1995-11-30 | 2003-01-14 | Micron Technology, Inc. | Structure for ESD protection in semiconductor chips |
US5719071A (en) * | 1995-12-22 | 1998-02-17 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad sturcture in an integrated circuit |
US5804846A (en) * | 1996-05-28 | 1998-09-08 | Harris Corporation | Process for forming a self-aligned raised source/drain MOS device and device therefrom |
US6316325B1 (en) * | 1998-11-13 | 2001-11-13 | United Microelectronics Corp. | Method for fabricating a thin film resistor |
US6392302B1 (en) | 1998-11-20 | 2002-05-21 | Micron Technology, Inc. | Polycide structure and method for forming polycide structure |
CN101145564B (zh) * | 2005-11-25 | 2012-08-29 | 香港科技大学 | 有源矩阵显示基板制备方法 |
CN103871882B (zh) * | 2012-12-17 | 2016-09-28 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
US20150171321A1 (en) | 2013-12-13 | 2015-06-18 | Micron Technology, Inc. | Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces |
US9984919B1 (en) | 2017-07-31 | 2018-05-29 | Globalfoundries Inc. | Inverted damascene interconnect structures |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1399163A (en) * | 1972-11-08 | 1975-06-25 | Ferranti Ltd | Methods of manufacturing semiconductor devices |
US4445266A (en) * | 1981-08-07 | 1984-05-01 | Mostek Corporation | MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance |
JPS60130844A (ja) * | 1983-12-20 | 1985-07-12 | Toshiba Corp | 半導体装置の製造方法 |
JPS60240123A (ja) * | 1984-05-15 | 1985-11-29 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS60245256A (ja) * | 1984-05-21 | 1985-12-05 | Fujitsu Ltd | 半導体装置 |
JPH0682758B2 (ja) * | 1984-06-15 | 1994-10-19 | ヒューレット・パッカード・カンパニー | 半導体集積回路の形成方法 |
US4589196A (en) * | 1984-10-11 | 1986-05-20 | Texas Instruments Incorporated | Contacts for VLSI devices using direct-reacted silicide |
DE3650077T2 (de) * | 1985-03-15 | 1995-02-23 | Hewlett Packard Co | Metallisches Verbindungssystem mit einer ebenen Fläche. |
EP0201250B1 (de) * | 1985-04-26 | 1992-01-29 | Fujitsu Limited | Verfahren zur Herstellung einer Kontaktanordnung für eine Halbleiteranordnung |
US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
US4630357A (en) * | 1985-08-02 | 1986-12-23 | Ncr Corporation | Method for forming improved contacts between interconnect layers of an integrated circuit |
US4660276A (en) * | 1985-08-12 | 1987-04-28 | Rca Corporation | Method of making a MOS field effect transistor in an integrated circuit |
US4751198A (en) * | 1985-09-11 | 1988-06-14 | Texas Instruments Incorporated | Process for making contacts and interconnections using direct-reacted silicide |
US4764484A (en) * | 1987-10-08 | 1988-08-16 | Standard Microsystems Corporation | Method for fabricating self-aligned, conformal metallization of semiconductor wafer |
-
1987
- 1987-08-27 US US07/090,301 patent/US4822749A/en not_active Expired - Lifetime
-
1988
- 1988-08-16 EP EP88201742A patent/EP0307021B1/de not_active Expired - Lifetime
- 1988-08-16 DE DE8888201742T patent/DE3872803T2/de not_active Expired - Fee Related
- 1988-08-24 JP JP63210418A patent/JP2598481B2/ja not_active Expired - Lifetime
- 1988-08-25 KR KR1019880010808A patent/KR970011263B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR890004404A (ko) | 1989-04-21 |
US4822749A (en) | 1989-04-18 |
JP2598481B2 (ja) | 1997-04-09 |
KR970011263B1 (ko) | 1997-07-08 |
DE3872803D1 (de) | 1992-08-20 |
JPS6472524A (en) | 1989-03-17 |
EP0307021B1 (de) | 1992-07-15 |
EP0307021A1 (de) | 1989-03-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8339 | Ceased/non-payment of the annual fee |