DE69526486T2 - Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung - Google Patents

Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung

Info

Publication number
DE69526486T2
DE69526486T2 DE69526486T DE69526486T DE69526486T2 DE 69526486 T2 DE69526486 T2 DE 69526486T2 DE 69526486 T DE69526486 T DE 69526486T DE 69526486 T DE69526486 T DE 69526486T DE 69526486 T2 DE69526486 T2 DE 69526486T2
Authority
DE
Germany
Prior art keywords
producing
integrated circuit
contact area
contact
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69526486T
Other languages
English (en)
Other versions
DE69526486D1 (de
Inventor
Tsiu C Chan
Frank R Bryant
Loi N Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69526486D1 publication Critical patent/DE69526486D1/de
Application granted granted Critical
Publication of DE69526486T2 publication Critical patent/DE69526486T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69526486T 1994-12-22 1995-11-30 Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung Expired - Fee Related DE69526486T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/361,760 US5702979A (en) 1994-05-31 1994-12-22 Method of forming a landing pad structure in an integrated circuit

Publications (2)

Publication Number Publication Date
DE69526486D1 DE69526486D1 (de) 2002-05-29
DE69526486T2 true DE69526486T2 (de) 2002-10-10

Family

ID=23423349

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69526486T Expired - Fee Related DE69526486T2 (de) 1994-12-22 1995-11-30 Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung

Country Status (4)

Country Link
US (3) US5702979A (de)
EP (1) EP0718879B1 (de)
JP (1) JPH08236624A (de)
DE (1) DE69526486T2 (de)

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US5854127A (en) * 1997-03-13 1998-12-29 Micron Technology, Inc. Method of forming a contact landing pad
US6083803A (en) 1998-02-27 2000-07-04 Micron Technology, Inc. Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances
US6369423B2 (en) * 1998-03-03 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device with a thin gate stack having a plurality of insulating layers
US6121094A (en) * 1998-07-21 2000-09-19 Advanced Micro Devices, Inc. Method of making a semiconductor device with a multi-level gate structure
US6140688A (en) * 1998-09-21 2000-10-31 Advanced Micro Devices Inc. Semiconductor device with self-aligned metal-containing gate
JP2000114522A (ja) * 1998-10-08 2000-04-21 Toshiba Corp 半導体装置及びその製造方法
US6288419B1 (en) * 1999-07-09 2001-09-11 Micron Technology, Inc. Low resistance gate flash memory
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US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
JP2002208695A (ja) * 2001-01-11 2002-07-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6706608B2 (en) * 2001-02-28 2004-03-16 Micron Technology, Inc. Memory cell capacitors having an over/under configuration
US6767778B2 (en) * 2002-08-29 2004-07-27 Micron Technology, Inc. Low dose super deep source/drain implant
US7462521B2 (en) * 2004-11-29 2008-12-09 Walker Andrew J Dual-gate device and method
DE102008043929A1 (de) * 2008-11-20 2010-05-27 Robert Bosch Gmbh Elektronisches Bauelement
KR102230194B1 (ko) 2014-04-14 2021-03-19 삼성전자주식회사 반도체 소자
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
US9397049B1 (en) 2015-08-10 2016-07-19 International Business Machines Corporation Gate tie-down enablement with inner spacer
US9768179B1 (en) * 2016-11-18 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Connection structures for routing misaligned metal lines between TCAM cells and periphery circuits
KR20220003870A (ko) 2020-07-02 2022-01-11 삼성전자주식회사 반도체 메모리 장치 및 그 제조 방법

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Also Published As

Publication number Publication date
DE69526486D1 (de) 2002-05-29
US5702979A (en) 1997-12-30
JPH08236624A (ja) 1996-09-13
USRE36938E (en) 2000-10-31
EP0718879A1 (de) 1996-06-26
EP0718879B1 (de) 2002-04-24
US5894160A (en) 1999-04-13

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee