JPH06105726B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH06105726B2
JPH06105726B2 JP1265135A JP26513589A JPH06105726B2 JP H06105726 B2 JPH06105726 B2 JP H06105726B2 JP 1265135 A JP1265135 A JP 1265135A JP 26513589 A JP26513589 A JP 26513589A JP H06105726 B2 JPH06105726 B2 JP H06105726B2
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JP
Japan
Prior art keywords
film
bonding pad
integrated circuit
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1265135A
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English (en)
Other versions
JPH03127843A (ja
Inventor
仁士 藤本
清昭 津村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1265135A priority Critical patent/JPH06105726B2/ja
Priority to US07/450,455 priority patent/US4984056A/en
Publication of JPH03127843A publication Critical patent/JPH03127843A/ja
Publication of JPH06105726B2 publication Critical patent/JPH06105726B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、半導体集積回路装置、特に、半導体基板表
面に形成された半導体装置のボンディングパッドの構造
に関し、相互結線作業（ワイヤボンド）時に安定してワ
イヤボンドを行うことができ、結線された結合部の信頼
性が高い半導体集積回路装置に関するものである。
［従来の技術］ 半導体基板に形成された半導体装置は、その表面に一変
が100μｍ程度の複数個のボンディングパッド部が形成
されており、このボンディングパッド部と外部リード間
とは金線又はアルミニウム線で相互に結線され電気的結
合が行われる。
最近の半導体集積回路装置は、高速化、パターン微細化
等が進んでおり、これを実現するものとして例えば第２
図に示す半導体集積回路装置がある。
第２図は例えば特開昭64−37031号公報に示された従来
の半導体集積回路装置のダイナミックメモリーにおける
一般的なボンディングパッドの下地構造を示す断面図で
ある。図において、半導体基板（１）上にフィールド酸
化膜（２）例えばSiO2膜が形成され、このフィールド酸
化膜（２）上にポリシリコン膜（多結晶シリコン）
（３）が形成されている。このポリシリコン膜（３）上
には、高融点金属のシリサイド膜例えばタングステンシ
リサイド（WSi）膜（４）が形成されている。これらの
ポリシリコン膜（３）及びタングステンシリサイド
（４）を合わせた複合膜はポリサイド膜と呼ばれ、ゲー
ト電極材料となる。このポリサイド膜を覆ってフィール
ド酸化膜（２）上に、耐湿性を向上させて金属細線
（９）の腐食を低減できる層間絶縁膜であるポロンリン
ケイ酸ガラス膜（以下、BPSG膜とする）（５）を形成す
る。次いで、ポリサイド膜の側部を覆うように、BPSG膜
（５）のボンディングパッド（７）を形成する部分のみ
をエッチングにより除去する。さらに、タングステンシ
リサイド膜（４）上に、バリアメタルであるTiN（窒化
チタン）膜（６）が被着される。TiN膜（６）は、回路
素子の特性向上の他、後述するボンディングパッド
（７）と金属細線（９）との金属接合部の劣化による断
線寿命を延ばす作用を持ち、さらに金属細線（９）から
の不純物金属の析出を防止することができる。TiN膜
（６）上には、例えばアルミニウム膜であるボンディン
グパッド（７）が形成されている。このボンディングパ
ッド（７）上に絶縁性保護膜（８）を被着させ、ボンデ
ィングパッド（７）となる部分を開孔させてその周囲を
覆うようにする。ボンディングパッド（７）と外部リー
ド（図示しない）との間は、金属細線（９）例えば金線
で接続されている。
従来の半導体集積回路装置は上述したように構成され、
ボンディングパッド（７）と金属細線（９）とを接続す
るワイヤボンド作業は、まず、キャピラリチップ（図示
しない）の先端に金属細線（９）を溶融させて密着さ
せ、このキャピラリチップで金属細線（９）の先端をボ
ンディングパッド（７）に押し当て、キャピラリチップ
自体に超音波振動を印加し、上方より荷重をかけること
により、ボンディングパッド（７）と金属細線（９）と
を金属拡散結合させている。
［発明が解決しようとする課題］ 上述したような半導体集積回路装置におけるボンディン
グパッドの下地構造では、ボンディング完了後にタング
ステンシリサイド膜（４）とポリシリコン膜（３）との
密着性が悪く、高温熱処理工程で生じる残留応力が作用
するため、これらの間で剥がれすなわちパッド剥がれが
生じるという問題点があった。
この発明は、このような問題点を解決するためになされ
たもので、パッド剥がれを防止することができ、かつ接
合部の劣化による寿命低下を防止することができるボン
ディングパッド構造を持った半導体集積回路装置を得る
ことを目的とする。
［課題を解決するための手段］ この発明に係る半導体集積回路装置は、剥がれの起き易
いポリサイド膜の代替として、TiN膜とフィールド酸化
膜との間にテトラエトキシオルトシラン膜（以下、TEOS
膜とする）を設けたものである。
［作用］ この発明においては、TiN膜とフィールド酸化膜との間
にTEOS膜を介在させることにより、これらの膜間の密着
強度を大幅に向上させることができる。
［実施例］ 第１図はこの発明の一実施例による半導体集積回路装置
におけるボンディングパッドの下地構造を示す断面図で
あり、（１）、（２）、（５）、（６）〜（８）は上述
した従来の半導体集積回路装置におけるものと全く同一
である。図において、半導体基板（１）上にフィールド
酸化膜（２）が形成され、このフィールド酸化膜（２）
上には層間絶縁膜例えばBPSG膜（５）が形成されてい
る。このBPSG膜（５）上には、液状のテトラエトキシオ
ルトシランを塗布して成長させたTEOS膜（10）が形成さ
れている。このTEOS膜（10）上に、ボンディングパッド
（７）の外周とほぼ同じ大きさの外周を持ったTiN膜
（６）が被着され、さらに、このTiN膜（６）上にボン
ディングパッド（７）が被着されている。これらのTiN
膜（６）及びボンディングパッド（７）は所定形状にパ
ターニングされた後、ボンディングパッド（７）上に絶
縁性保護膜（８）が被着されている。次いで、ボンディ
ングパッド（７）の側部を覆うように絶縁性保護膜
（８）の所定部分をエッチング等により開孔させる。以
下、従来の半導体集積回路装置と同様に、ボンディング
パッド（７）と金属細線（図示しない）とをワイヤボン
ド作業する。
上述したように構成された半導体集積回路装置において
は、BPSG膜（５）とTiN膜（６）との間にTEOS膜（10）
が介在しているので、これらの膜間の密着強度を大幅に
向上させることができる。従って、ワイヤボンド作業後
のボンディングパッド（７）の下地からの剥がれが防止
でき、歩留まりを向上させることができる。さらに、パ
ッド剥がれを防止することができ、接合部の劣化による
寿命低下を防止することができる。
［発明の効果］ この発明は、以上説明したとおり、TiN膜とフィールド
酸化膜との間にTEOS膜を介在させたので、パッド剥がれ
を防止することができ、かつ接合部の劣化による寿命低
下を防止することができるという効果を奏する。
【図面の簡単な説明】
第１図はこの発明の一実施例による半導体集積回路装置
におけるボンディングパッドの下地構造を示す断面図、
第２図は従来の半導体集積回路装置におけるボンディン
グパッドの下地構造を示す断面図である。 図において、（１）は半導体基板、（２）はフィールド
酸化膜、（５）はBPSG膜、（６）はTiN膜、（７）はボ
ンディングパッド、（８）は絶縁性保護膜、（10）はTE
OS膜である。 なお、各図中、同一符号は同一または相当部分を示す。

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】半導体基板と、この半導体基板上に形成さ
    れたフィールド酸化膜と、このフィールド酸化膜上に形
    成された絶縁膜と、この絶縁膜上に形成されたテトラエ
    トキシオルトシラン膜と、このテトラエトキシオルトシ
    ラン膜上に被着されボンディングパッドの外周とほぼ同
    じ大きさの外周を持つ窒化チタン膜と、この窒化チタン
    膜上に被着されたボンディングパッドと、このボンディ
    ングパッドの上面に開孔部を有するように上記窒化チタ
    ン膜及びボンディングパッドの側部を覆って上記テトラ
    エトキシオルトシラン膜上に形成された絶縁性保護膜と
    を備えたことを特徴とする半導体集積回路装置。
JP1265135A 1989-10-13 1989-10-13 半導体集積回路装置 Expired - Lifetime JPH06105726B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1265135A JPH06105726B2 (ja) 1989-10-13 1989-10-13 半導体集積回路装置
US07/450,455 US4984056A (en) 1989-10-13 1989-12-14 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1265135A JPH06105726B2 (ja) 1989-10-13 1989-10-13 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPH03127843A JPH03127843A (ja) 1991-05-30
JPH06105726B2 true JPH06105726B2 (ja) 1994-12-21

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Country Status (2)

Country Link
US (1) US4984056A (ja)
JP (1) JPH06105726B2 (ja)

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JP2596331B2 (ja) * 1993-09-08 1997-04-02 日本電気株式会社 半導体装置およびその製造方法
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5633196A (en) * 1994-05-31 1997-05-27 Sgs-Thomson Microelectronics, Inc. Method of forming a barrier and landing pad structure in an integrated circuit
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
US5719071A (en) * 1995-12-22 1998-02-17 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad sturcture in an integrated circuit
KR100295240B1 (ko) 1997-04-24 2001-11-30 마찌다 가쯔히꼬 반도체장치
JP3327244B2 (ja) * 1999-03-12 2002-09-24 日本電気株式会社 半導体装置
KR100403619B1 (ko) * 2001-02-21 2003-10-30 삼성전자주식회사 열적/기계적 스트레스에 저항성이 강한 반도체 소자의 본드패드 및 그 형성방법
JP2007035909A (ja) * 2005-07-27 2007-02-08 Seiko Epson Corp 電子デバイスおよび電子デバイスの製造方法
WO2010098500A1 (ja) * 2009-02-27 2010-09-02 三洋電機株式会社 半導体装置及びその製造方法
JP2014123611A (ja) * 2012-12-20 2014-07-03 Denso Corp 半導体装置

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Also Published As

Publication number Publication date
JPH03127843A (ja) 1991-05-30
US4984056A (en) 1991-01-08

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