DE3855889T2 - Ein verfahren zur herstellung selbstausrichtender halbleiteranordnungen - Google Patents

Ein verfahren zur herstellung selbstausrichtender halbleiteranordnungen

Info

Publication number
DE3855889T2
DE3855889T2 DE3855889T DE3855889T DE3855889T2 DE 3855889 T2 DE3855889 T2 DE 3855889T2 DE 3855889 T DE3855889 T DE 3855889T DE 3855889 T DE3855889 T DE 3855889T DE 3855889 T2 DE3855889 T2 DE 3855889T2
Authority
DE
Germany
Prior art keywords
contacts
layer
polysilicon
layer structure
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855889T
Other languages
English (en)
Other versions
DE3855889D1 (de
Inventor
Jacob Haskell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE3855889D1 publication Critical patent/DE3855889D1/de
Application granted granted Critical
Publication of DE3855889T2 publication Critical patent/DE3855889T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE3855889T 1987-12-02 1988-12-02 Ein verfahren zur herstellung selbstausrichtender halbleiteranordnungen Expired - Fee Related DE3855889T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12782087A 1987-12-02 1987-12-02
PCT/US1988/004291 WO1989005516A1 (en) 1987-12-02 1988-12-02 Self-aligned semiconductor devices

Publications (2)

Publication Number Publication Date
DE3855889D1 DE3855889D1 (de) 1997-05-28
DE3855889T2 true DE3855889T2 (de) 1997-08-07

Family

ID=22432120

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855889T Expired - Fee Related DE3855889T2 (de) 1987-12-02 1988-12-02 Ein verfahren zur herstellung selbstausrichtender halbleiteranordnungen

Country Status (5)

Country Link
EP (1) EP0344292B1 (de)
JP (1) JPH02502417A (de)
AT (1) ATE152287T1 (de)
DE (1) DE3855889T2 (de)
WO (1) WO1989005516A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151387A (en) * 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
US8803203B2 (en) 2010-02-26 2014-08-12 Eastman Kodak Company Transistor including reentrant profile
US7923313B1 (en) 2010-02-26 2011-04-12 Eastman Kodak Company Method of making transistor including reentrant profile
US8847232B2 (en) 2011-01-07 2014-09-30 Eastman Kodak Company Transistor including reduced channel length
US8304347B2 (en) 2011-01-07 2012-11-06 Eastman Kodak Company Actuating transistor including multiple reentrant profiles
US8847226B2 (en) 2011-01-07 2014-09-30 Eastman Kodak Company Transistor including multiple reentrant profiles
US8409937B2 (en) 2011-01-07 2013-04-02 Eastman Kodak Company Producing transistor including multi-layer reentrant profile
US8383469B2 (en) 2011-01-07 2013-02-26 Eastman Kodak Company Producing transistor including reduced channel length
US8338291B2 (en) 2011-01-07 2012-12-25 Eastman Kodak Company Producing transistor including multiple reentrant profiles
US7985684B1 (en) 2011-01-07 2011-07-26 Eastman Kodak Company Actuating transistor including reduced channel length
US8492769B2 (en) 2011-01-07 2013-07-23 Eastman Kodak Company Transistor including multi-layer reentrant profile
US8617942B2 (en) 2011-08-26 2013-12-31 Eastman Kodak Company Producing transistor including single layer reentrant profile
US8592909B2 (en) 2011-08-26 2013-11-26 Eastman Kodak Company Transistor including single layer reentrant profile
US8637355B2 (en) 2011-08-26 2014-01-28 Eastman Kodak Company Actuating transistor including single layer reentrant profile
US8865576B2 (en) 2011-09-29 2014-10-21 Eastman Kodak Company Producing vertical transistor having reduced parasitic capacitance
US8803227B2 (en) 2011-09-29 2014-08-12 Eastman Kodak Company Vertical transistor having reduced parasitic capacitance

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5420959B2 (de) * 1974-01-23 1979-07-26
US4016587A (en) * 1974-12-03 1977-04-05 International Business Machines Corporation Raised source and drain IGFET device and method
JPS5254694A (en) * 1975-10-31 1977-05-04 Mitsubishi Kakoki Kk Regeneration of catalysts for desulfurizing active carbons
JPS5379783A (en) * 1976-12-24 1978-07-14 Toyo Rubber Chem Ind Co Ltd Production of adsorbent
NL190710C (nl) * 1978-02-10 1994-07-01 Nec Corp Geintegreerde halfgeleiderketen.
JPS54140483A (en) * 1978-04-21 1979-10-31 Nec Corp Semiconductor device
JPS55116443A (en) * 1979-02-28 1980-09-08 Agency Of Ind Science & Technol Regeneration of dry type simultaneous desulfurization and denitrification catalyst
JPS6037047B2 (ja) * 1979-03-09 1985-08-23 住友重機械工業株式会社 脱硫用活性炭の再生法
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
JPS57176746A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit and manufacture thereof
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
JPS59150536A (ja) * 1983-02-16 1984-08-28 Ishikawajima Harima Heavy Ind Co Ltd 脱硫用活性炭の再生方法

Also Published As

Publication number Publication date
ATE152287T1 (de) 1997-05-15
EP0344292A4 (de) 1990-05-14
JPH02502417A (ja) 1990-08-02
EP0344292B1 (de) 1997-04-23
DE3855889D1 (de) 1997-05-28
EP0344292A1 (de) 1989-12-06
WO1989005516A1 (en) 1989-06-15

Similar Documents

Publication Publication Date Title
DE3855889T2 (de) Ein verfahren zur herstellung selbstausrichtender halbleiteranordnungen
EP0161740B1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
EP0044950B1 (de) Verfahren zur Herstellung einer Martix von untereinander verbundenen Halbleiterbauelementen
JPS6437865A (en) Semiconductor memory device and its manufacture
EP0366587A3 (de) Halbleiteranordnungen mit eng beabstandeten Gebieten, hergestellt unter Verwendung eines selbstausrichtenden Umkehrbildverfahrens
EP0386947A3 (de) Dynamische Speicherzelle mit wahlfreiem Zugriff
DE3486364D1 (de) Verfahren zum Herstellen von MOS-Transistoren mit flachen Source/Drain-Gebieten, kurzen Kanallängen und einer selbstjustierten, aus einem Metallsilizid bestehenden Kontaktierungsebene.
KR960012585B1 (en) Transistor structure and the method for manufacturing the same
WO2002080275A3 (de) Speicherzellenarrays und deren herstellungssverfahren
EP0797245A3 (de) Verfahren zur Herstellung von einem vertikalen MOS-Halbleiterbauelement
ATE54227T1 (de) Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen.
FR2428324A1 (fr) Circuits integres a tres grande echelle et leur procede de realisation par alignement automatique de contacts
TW340960B (en) Process for forming deep trench drams with sub-groundrule gates
DE3687973D1 (de) Verfahren zum gleichzeitigen herstellen von bipolaren und komplementaeren mos-transistoren auf einem gemeinsamen siliziumsubstrat.
WO1997049134A3 (en) Soi-transistor circuitry employing soi-transistors and method of manufacture thereof
TW363270B (en) Buried bit line DRAM cell and manufacturing method thereof
DE59309324D1 (de) Herstellverfahren für ein selbstjustiertes Kontaktloch und Halbleiterstruktur
TW365697B (en) Etching method of improving of self-aligned contact
TW288200B (en) Semiconductor device and process thereof
EP0282407A3 (de) Halbleiteranordnung mit vielfachen Quanten-Potentialtöpfen
DE59506590D1 (de) Halbleiteranordnung mit selbstjustierten Kontakten und Verfahren zu ihrer Herstellung
EP0307598A3 (en) Method of fabricating a bipolar semiconductor device with silicide contacts
EP0314399A3 (de) Vergrabene Zenerdiode und Verfahren zu deren Herstellung
DE59206456D1 (de) Verfahren zur Herstellung eines MOS-Transistors
ATE256340T1 (de) Verfahren zur herstellung einer vergrabenen, lateral isolierten zone erhöhter leitfähigkeit in einem halbleitersubstrat

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee