US4884120A - Semiconductor device and method for making the same - Google Patents
Semiconductor device and method for making the same Download PDFInfo
- Publication number
- US4884120A US4884120A US07/016,787 US1678787A US4884120A US 4884120 A US4884120 A US 4884120A US 1678787 A US1678787 A US 1678787A US 4884120 A US4884120 A US 4884120A
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- United States
- Prior art keywords
- interconnection
- film
- layer
- semiconductor device
- hole
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- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 41
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 41
- 230000000149 penetrating effect Effects 0.000 claims description 9
- 238000009835 boiling Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 239000008367 deionised water Substances 0.000 claims description 2
- 229910021641 deionized water Inorganic materials 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims 3
- 238000009413 insulation Methods 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 74
- 239000011229 interlayer Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- LKTZODAHLMBGLG-UHFFFAOYSA-N alumanylidynesilicon;$l^{2}-alumanylidenesilylidenealuminum Chemical compound [Si]#[Al].[Si]#[Al].[Al]=[Si]=[Al] LKTZODAHLMBGLG-UHFFFAOYSA-N 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
Definitions
- the present invention relates to a semiconductor device and the method for making the same. More specifically, the present invention relates to a interconnection structure and the method for making the same for improving electrical contact between the interconnection of a first layer and the interconnection of a second layer in a semiconductor device having multilayer interconnection structure in which a contact hole for the electrical contact between the interconnection of the first layer and the surface of the semiconductor substrate and a through hole for the electrical contact between the interconnection of the first layer and the interconnection of the second layer are formed in the same region in order to improve the degree of integration.
- FIGS. 1A and 1B are cross-sectional side views schematically showing the steps of manufacturing the above described multilayered interconnection of a semiconductor device.
- the method for manufacturing the conventional interconnection in a semiconductor device will be hereinafter described with reference to FIGS. 1A and 1B.
- An insulating film such as PSG film (phosphorous doped silicon oxide film) is formed by e.g. CVD method (chemical vapor deposition) on the entire surface of a silicon semiconductor substrate (hereinafter simply referred to as a silicon substrate) on which circuit elements etc. (not shown) are formed. Then a resist film (not shown) is applied on the entire surface of the insulating film 2, and then it is exposed and etched to be patterned into a predetermined form.
- CVD method chemical vapor deposition
- a penetrating hole (hereinafter referred to as a contact hole) 10 deep enough to reach the surface of the silicon substrate 1 is formed in a predetermined region of the insulating film 2 by dry etching or wet etching using the patterned resist film (not shown) as a mask.
- an aluminum film is deposited to cover the insulating film 2 and the contact hole 10 by sputtering method or the like. This aluminum film is patterned by dry etching or wet etching using a resist film (not shown) as a mask to form a first layer aluminum interconnection film 3 having a predetermined form. Then an interlayer insulating film 5 is formed over the entire exposed surface by using the CVD method.
- a silicon nitride film, silicon oxide film or the like may be used as the interlayer insulating film 5.
- a patterned resist film (not shown) is formed on the interlayer insulating film 5.
- a penetrating hole (hereinafter simply referred to as a through hole) 11 reaching the surface of the first layer aluminum interconnection film 3 is formed in a predetermined region of the interlayer insulating film 5 by dry etching or wet etching, using the patterned resist film as a mask.
- the through hole 11 is formed such that it overlaps with the contact hole 10 in planar layout.
- the through hole becomes a contact hole for making electrical contact between the first layer aluminum interconnection 3 and the second layer aluminum interconnection which in turn will be formed in the following steps.
- FIG. 1B An aluminum film to be the second layer interconnection film will be formed on the entire exposed surface by the sputtering method or the like. This aluminum film is patterned by dry etching or wet etching into a predetermined shape to form the second layer aluminum interconnection film 6 for electrically connecting the first layer aluminum inerconnection film 3 with other circuit elements. As shown in FIG. 1B, since the contact hole 10 and the through hole 11 are formed in the same region, the effective aspect ratio of the through hole (the ratio of the depth to the width of the through hole 11) becomes large, so that the step coverage at the through hole 11 with the second layer aluminum interconnection film 6 is not satisfactory.
- the interlayer insulating film 5 when the interlayer insulating film 5 is made thin to minimize the effective aspect ratio of the through hole 11 at the interlayer insulating film 5 in order to prevent the above described problem, the interlayer insulating film 5 can not fully effect its function, causing another problem that sufficient electrical insulation can not be kept between the second layer aluminum interconnection film 6 and the underlying first layer aluminum interconnection film or the silicon substrate 1.
- An object of the present invention is to provide a semiconductor device and the method for making the same for eliminating the above described drawbacks of a conventional semiconductor device wherein the excellent electrical contact can be readily and surely made between the first layer interconnection and the second layer interconnection even in the case where the through hole for the second layer interconnection is provided directly above the contact hole portion for the first layer interconnection.
- hillocks are concentratedly formed on the first layer interconnection film which is formed in the contact hole for making electrical contact of the first layer interconnection with the semiconductor substrate.
- the method for making the semiconductor device according to the present invention comprises the steps of forming an oxide film through selective chemical conversion of the first layer interconnection film which is more rigid than the first layer interconnection film on the region of the first layer interconnection film except the region on which the through hole for the second layer interconnection is to be formed, and forming hillocks concentratedly by heat processing at the region of the first layer interconnection film where the through hole for the second layer interconnection film is to be formed.
- the rigid oxide film selectively formed on the first layer interconnection film suppresses the generation of hillocks at the regions except that region where the through hole for the second layer interconnection film is formed while it generates hillocks concentratedly on that region of the first layer interconnection film where the through hole is formed through heat processing.
- the height of the formed hillocks is controlled by the parameters such as the thickness of the rigid oxide film, formed area thereof and the condition of the heat processing to compensate for the step at that region of the first layer interconnection film where the through hole for the second layer interconnection is formed, thus minimizing the effective aspect ratio of the through hole for the second layer interconnection film.
- FIGS. 1A and 1B are cross sectional views showing the steps of forming interconnections in the process of manufacturing a semiconductor device having a conventional multilayered interconnection structure.
- FIGS. 2A to 2D are cross sectional views showing the steps of forming interconnections in the process of manufacturing a semiconductor device having multilayered interconnection structure according to one embodiment of the present invention.
- FIGS. 2A to 2D are cross sectional views showing the steps of forming interconnection according to the manufacturing method of one embodiment of the present invention.
- the method for making the semiconductor device according to one embodiment of the present invention will be hereinafter described with reference to FIGS. 2A to 2D.
- an insulating film 2 of e.g. PSG film having a contact hole reaching the surface of the substrate 1 in a predetermined region and the first layer aluminum interconnection film 3 are formed on the surface of the semiconductor substrate 1 of e.g. silicon using a conventional manufacturing method. Namely, an insulating film 2 is formed on the surface of the semiconductor substrate 1 by the CVD (chemical vapor deposition) method etc., and a patterned resist film (not shown) is formed on the insulating film 2. Then a contact hole 10 reaching the surface of the silicon substrate 1 is formed in the insulating film 2 by dry etching or wet etching using the patterned resist film as a mask. Then an aluminum film is formed by e.g.
- CVD chemical vapor deposition
- the film is patterned into a predetermined shape to form the first layer aluminum interconnection film 3.
- a step is formed at the first layer aluminum interconnection film 3 in the region of the contact hole 10 under the influence of the step of the insulating film 2 at the contact hole 10.
- a resist film (not shown) patterned by using e.g. the photolithography is formed only on that region of the first layer interconnection film 3 where the through hole for the second layer interconnection is to be formed in the following steps.
- Chemical conversion processing i.e. boiling process for several to 20 minutes in the heated D.I. water (deionized water) of more than 40° C in this embodiment, is performed on the first layer aluminum interconnection film 3 using the patterned resist film as a mask to form an alumina film 4, which is an oxide of aluminum, on a predetermined region of the first layer aluminum interconnection film 3.
- the alumina film 4 is rigid enough to be effective in suppressing the generation of hillocks on the aluminum, hillocks 20 are generated concentratedly on the region where the alumina film 4 is not formed, that is, the region where the through hole for the second layer interconnection film is to be formed.
- the height of the hillock 20 can be suitably adjusted by suitably controlling the thickness of the alumina film 4, the area of the first layer aluminum interconnection film covered by the alumina film 4, the conditions of heat processing and so on. Therefore, the step formed at the region of the contact hole 10 of the first layer aluminum interconnection film 3 can be compensated.
- an interlayer insulating film 5 and the second layer aluminum interconnection film 6 are formed in a conventional manner. Namely, an insulating film 5 of e.g. silicon nitride film or silicon oxide film is formed by the CVD method etc., over the entire exposed surface, and then the film is patterned to form a through hole 11 for the second layer aluminum interconnection at a predetermined region on the contact hole 10. Then an aluminum film is formed by e.g. the sputtering method over the interlayer insulating film 5 and the through hole 11, and then, this aluminum film is patterned to form the second layer interconnection film 6. Different from the conventional semiconductor device shown in FIG.
- the effective aspect ratio of the through hole 11 for the second layer aluminum interconnection film 6 becomes small by virtue of the protruding hillocks formed in the region of the contact hole 10 of the first layer aluminum interconnection film 3. Consequently, the second layer aluminum interconnection film 6 can be formed in the region of the through hole 11 with good coverage.
- a good electrical contact between the first layer aluminum interconnection film 3 and the second layer aluminum interconnection 6 is provided and therefore an electrical contact of the first layer interconnection with the second layer interconnection can be readily and surely made even in such a structure that the through hole for the second layer interconnection is formed directly above the contact hole region of the first layer interconnection, realizing a semiconductor device having high degree of integration.
- the material is not limited to that, an aluminum alloys such as aluminum silicide may be used to obtain the same effect.
- refractory metals can be used as the material of interconnections to obtain the same effect as described above, provided that the oxide film thereof formed by a suitable chemical conversion process is more rigid than the underlying refractory metal.
- hillocks are concentratedly formed in the contact hole portion for the first layer interconnection by a suitable chemical conversion process over the first layer interconnection to compensate for the step at the contact hole region of the first layer interconnection film, so that the effective aspect ratio of the through hole for the second layer interconnection becomes small and the electrical contact of the first layer interconnection with the second layer interconnection can be readily and surely made even in a semiconductor device having the contact hole for the first layer interconnection and the through hole for the second layer interconnection formed in the same region, and thus a semiconductor device having high degree of integration can be implemented.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61-37785 | 1986-02-20 | ||
JP61037785A JPS62194644A (en) | 1986-02-20 | 1986-02-20 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US4884120A true US4884120A (en) | 1989-11-28 |
Family
ID=12507140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/016,787 Expired - Fee Related US4884120A (en) | 1986-02-20 | 1987-02-20 | Semiconductor device and method for making the same |
Country Status (4)
Country | Link |
---|---|
US (1) | US4884120A (en) |
JP (1) | JPS62194644A (en) |
KR (1) | KR900007757B1 (en) |
DE (1) | DE3705152A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4984060A (en) * | 1987-09-24 | 1991-01-08 | Tadahiro Ohmi | Semiconductor device wirings with hillocks |
US5252382A (en) * | 1991-09-03 | 1993-10-12 | Cornell Research Foundation, Inc. | Interconnect structures having patterned interfaces to minimize stress migration and related electromigration damages |
US5371047A (en) * | 1992-10-30 | 1994-12-06 | International Business Machines Corporation | Chip interconnection having a breathable etch stop layer |
US5439731A (en) * | 1994-03-11 | 1995-08-08 | Cornell Research Goundation, Inc. | Interconnect structures containing blocked segments to minimize stress migration and electromigration damage |
US5679982A (en) * | 1993-02-24 | 1997-10-21 | Intel Corporation | Barrier against metal diffusion |
US5897376A (en) * | 1993-09-20 | 1999-04-27 | Seiko Instruments Inc. | Method of manufacturing a semiconductor device having a reflection reducing film |
US6087710A (en) * | 1996-01-26 | 2000-07-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having self-aligned contacts |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4140330C1 (en) * | 1991-12-06 | 1993-03-18 | Texas Instruments Deutschland Gmbh, 8050 Freising, De |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3866311A (en) * | 1971-06-14 | 1975-02-18 | Nat Semiconductor Corp | Method of providing electrically isolated overlapping metallic conductors |
DE3109801A1 (en) * | 1981-03-13 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Process for producing semiconductor components |
GB2128025A (en) * | 1982-09-24 | 1984-04-18 | Hitachi Ltd | Protective electrode for electronic device |
JPS61280638A (en) * | 1985-06-06 | 1986-12-11 | Toshiba Corp | Manufacture of semiconductor device |
US4698125A (en) * | 1983-06-16 | 1987-10-06 | Plessey Overseas Limited | Method of producing a layered structure |
US4707457A (en) * | 1986-04-03 | 1987-11-17 | Advanced Micro Devices, Inc. | Method for making improved contact for integrated circuit structure |
US4734754A (en) * | 1984-05-07 | 1988-03-29 | Nec Corporation | Semiconductor device having improved structure of multi-wiring layers |
JPH064258A (en) * | 1992-06-23 | 1994-01-14 | Toshiba Corp | Information processor |
-
1986
- 1986-02-20 JP JP61037785A patent/JPS62194644A/en active Pending
- 1986-11-27 KR KR1019860010041A patent/KR900007757B1/en not_active IP Right Cessation
-
1987
- 1987-02-18 DE DE19873705152 patent/DE3705152A1/en active Granted
- 1987-02-20 US US07/016,787 patent/US4884120A/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3866311A (en) * | 1971-06-14 | 1975-02-18 | Nat Semiconductor Corp | Method of providing electrically isolated overlapping metallic conductors |
DE3109801A1 (en) * | 1981-03-13 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Process for producing semiconductor components |
GB2128025A (en) * | 1982-09-24 | 1984-04-18 | Hitachi Ltd | Protective electrode for electronic device |
US4698125A (en) * | 1983-06-16 | 1987-10-06 | Plessey Overseas Limited | Method of producing a layered structure |
US4734754A (en) * | 1984-05-07 | 1988-03-29 | Nec Corporation | Semiconductor device having improved structure of multi-wiring layers |
JPS61280638A (en) * | 1985-06-06 | 1986-12-11 | Toshiba Corp | Manufacture of semiconductor device |
EP0216017A2 (en) * | 1985-06-06 | 1987-04-01 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including forming a multi-level interconnection layer |
US4707457A (en) * | 1986-04-03 | 1987-11-17 | Advanced Micro Devices, Inc. | Method for making improved contact for integrated circuit structure |
JPH064258A (en) * | 1992-06-23 | 1994-01-14 | Toshiba Corp | Information processor |
Non-Patent Citations (6)
Title |
---|
"Patents Abstracts of Japan", vol. 10, no. 54 (mar. 4, 1986). |
Cadien and Losee, "A Method for Eliminating Hillocks in Integrated-Circuit Metallizations", J. Vac. Sci. Tecnol. B2(1), (jan.-Mar. 1984) pp. 82-83. |
Cadien and Losee, A Method for Eliminating Hillocks in Integrated Circuit Metallizations , J. Vac. Sci. Tecnol. B2(1), (jan. Mar. 1984) pp. 82 83. * |
D. Culver et al., "Modeling of Metal Step Coverage for Minimum Feature Size Contacts and Vias", IEEE 1985 V-MIC Conference CH 219-2185/0000-03994, 01.00, pp. 399-407. |
D. Culver et al., Modeling of Metal Step Coverage for Minimum Feature Size Contacts and Vias , IEEE 1985 V MIC Conference CH 219 2185/0000 03994, 01.00, pp. 399 407. * |
Patents Abstracts of Japan , vol. 10, no. 54 (mar. 4, 1986). * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4984060A (en) * | 1987-09-24 | 1991-01-08 | Tadahiro Ohmi | Semiconductor device wirings with hillocks |
US5252382A (en) * | 1991-09-03 | 1993-10-12 | Cornell Research Foundation, Inc. | Interconnect structures having patterned interfaces to minimize stress migration and related electromigration damages |
US5371047A (en) * | 1992-10-30 | 1994-12-06 | International Business Machines Corporation | Chip interconnection having a breathable etch stop layer |
US5679982A (en) * | 1993-02-24 | 1997-10-21 | Intel Corporation | Barrier against metal diffusion |
US5783483A (en) * | 1993-02-24 | 1998-07-21 | Intel Corporation | Method of fabricating a barrier against metal diffusion |
US5897376A (en) * | 1993-09-20 | 1999-04-27 | Seiko Instruments Inc. | Method of manufacturing a semiconductor device having a reflection reducing film |
US5439731A (en) * | 1994-03-11 | 1995-08-08 | Cornell Research Goundation, Inc. | Interconnect structures containing blocked segments to minimize stress migration and electromigration damage |
US6087710A (en) * | 1996-01-26 | 2000-07-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having self-aligned contacts |
US6268278B1 (en) | 1996-01-26 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing process thereof |
US6573171B2 (en) | 1996-01-26 | 2003-06-03 | Mitsubishi Electric Corp | Semiconductor device and manufacturing process thereof |
Also Published As
Publication number | Publication date |
---|---|
DE3705152C2 (en) | 1989-07-20 |
JPS62194644A (en) | 1987-08-27 |
KR900007757B1 (en) | 1990-10-19 |
DE3705152A1 (en) | 1987-08-27 |
KR870008388A (en) | 1987-09-26 |
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